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  power bank flash mcu HT45F4N/ht45fh4n revision: v1.30 date: de?e??e? 1?? ?01? de?e??e? 1?? ?01?
rev. 1.30 ? de?e??e? 1?? ?01? rev. 1.30 3 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu table of contents eates cpu featu?es ......................................................................................................................... ? pe?iphe?al featu?es ................................................................................................................. ? gene?al des??iption ......................................................................................... 7 sele?tion ta?le ................................................................................................. 8 blo?k diag?a? .................................................................................................. 8 pin assign?ent ................................................................................................ 9 pin des??iptions ............................................................................................. 11 a?solute maxi?u? ratings .......................................................................... 17 d.c. cha?a?te?isti?s ....................................................................................... 18 a.c. cha?a?te?isti?s ....................................................................................... 19 scom ele?t?i?al cha?a?te?isti?s .................................................................. ?0 lvd & lvr ele?t?i?al cha?a?te?isti?s .......................................................... ?0 a/d conve?te? ele?t?i?al cha?a?te?isti?s ..................................................... ?1 ove? cu??ent ci??uit ele?t?i?al cha?a?te?isti?s .......................................... ?1 ove?/unde? voltage ci??uit ele?t?i?al cha?a?te?isti?s ............................... ?? usb cha?ge/dis?ha?ge dete?tion ele?t?i?al cha?a?te?isti?s .................... ?? ldo regulato? ele?t?i?al cha?a?te?isti?s ................................................... ?3 level conve?te? ele?t?i?al cha?a?te?isti?s .................................................. ?3 powe? on reset ele?t?i?al cha?a?te?isti?s .................................................. ?3 syste? a??hite?tu?e ...................................................................................... ?? clo?king and pipelining ......................................................................................................... ?? p?og?a? counte? ................................................................................................................... ?5 sta?k ..................................................................................................................................... ?? a?ith?eti? and logi? unit C alu ........................................................................................... ?? flash p?og?a? me?o?y ................................................................................. ?7 st?u?tu?e ................................................................................................................................ ?7 spe? ial ve?to?s ..................................................................................................................... ?7 look-up ta ?le ........................................................................................................................ ?8 ta ?le p?og?a? exa?ple ........................................................................................................ ?8 in ci??uit p?og?a??ing ......................................................................................................... ?9 on-chip de?ug suppo?t C ocds ......................................................................................... 30 ram data me?o?y ......................................................................................... 31 st?u?tu?e ................................................................................................................................ 31 spe?ial fun?tion registe? des??iption ........................................................ 33 indi?e? t add?essing registe?s C iar0? iar1 ......................................................................... 33 me?o?y pointe?s C mp0? mp1 .............................................................................................. 33 bank pointe? C bp ................................................................................................................. 3?
rev. 1.30 ? de?e??e? 1?? ?01? rev. 1.30 3 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu a??u?ulato? C acc ............................................................................................................... 3? p?og?a? counte? low registe? C pcl .................................................................................. 3? look-up ta ? le registe? s C tblp ? tbhp ? tblh ..................................................................... 3? status registe? C status .................................................................................................... 35 eeprom data memory .................................................................................. 37 eeprom data me?o?y st?u?tu?e ........................................................................................ 37 eeprom registe?s .............................................................................................................. 37 reading data f?o? the eeprom ........................................................................................ 39 w ?iting data to the eeprom ................................................................................................ 39 w ?ite p?ote?tion ..................................................................................................................... 39 eeprom inte??upt ................................................................................................................ 39 p?og?a??ing conside?ations ................................................................................................ ?0 oscillator ........................................................................................................ 41 os?illato? ove?view ............................................................................................................... ?1 system clock confgurations ................................................................................................ ?1 inte?nal rc os?illato? C hirc ............................................................................................... ?? inte?nal 3?khz os?illato? C lirc ........................................................................................... ?? operating modes and system clocks ......................................................... 42 syste? clo?ks ...................................................................................................................... ?? syste? ope?ation modes ...................................................................................................... ?3 cont?ol registe? .................................................................................................................... ?5 ope?ating mode swit?hing ................................................................................................... ?7 stand?y cu??ent conside?ations ........................................................................................... 50 wake-up ................................................................................................................................ 50 watchdog timer ............................................................................................. 51 wat ? hdog ti?e? clo?k sou??e .............................................................................................. 51 wat ? hdog ti?e? cont?ol registe? ......................................................................................... 51 wat ? hdog ti?e? ope?ation ................................................................................................... 5? reset and initialisation .................................................................................. 53 reset fun?tions .................................................................................................................... 53 reset initial conditions ......................................................................................................... 5? input/output ports ......................................................................................... 59 pull-high resisto?s ................................................................................................................ 59 po? t a wake-up ..................................................................................................................... ?0 i/o po?t cont?ol registe?s ..................................................................................................... ?1 pin-?e?apping fun?tions ...................................................................................................... ?? pin-?e?apping registe? ........................................................................................................ ?? i/o pin st?u?tu?es .................................................................................................................. ?? p?og?a??ing conside?ations ................................................................................................ ?5 timer modules C tm ...................................................................................... 66 int?odu?tion ........................................................................................................................... ?? tm ope?ation ........................................................................................................................ ?? tm clo?k sou??e ................................................................................................................... ??
rev. 1.30 ? de?e??e? 1?? ?01? rev. 1.30 5 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu tm inte??upts ......................................................................................................................... ?7 tm exte?nal pins ................................................................................................................... ?7 tm input/output pin cont?ol registe? ................................................................................... ?7 p?og?a??ing conside?ations ................................................................................................ 7? standard type tm C stm .............................................................................. 75 standa? d tm ope?ation ......................................................................................................... 75 standa? d type tm registe? des??iption ............................................................................... 7? standa? d type tm ope? ating modes .................................................................................... 80 co?pa?e output mode .......................................................................................................... 80 ti ?e?/counte? mode ............................................................................................................. 83 pwm output mode ................................................................................................................ 83 single pulse output mode .................................................................................................... 8? captu?e input mode .............................................................................................................. 88 periodic type tm C ptm ................................................................................ 90 pe?iodi? tm ope?ation .......................................................................................................... 90 pe?iodi? type tm registe? des??iption ................................................................................. 91 pe?iodi? type tm ope? ating modes ...................................................................................... 95 co?pa?e mat?h output mode ............................................................................................... 95 ti ?e?/counte? mode ............................................................................................................. 98 pwm output mode ................................................................................................................ 98 single pulse output mode .................................................................................................. 100 captu?e input mode ............................................................................................................ 10? analog to digital converter ........................................................................ 104 a/d ove?view ...................................................................................................................... 10? a/d conve?te? registe? des??iption .................................................................................... 105 a/d conve?te? data registe? s C adrl? adrh ................................................................... 105 a/d conve ?te? cont? ol registe? s C adcr0? adcr1? acerl? acerh .............................. 105 a/d ope?ation ...................................................................................................................... 110 a/d input pins ...................................................................................................................... 111 su??a? y of a/d conve?sion steps ...................................................................................... 11 ? p?og?a??ing conside?ations ............................................................................................... 113 a/d t ?ansfe? fun?tion .......................................................................................................... 113 a/d p?og?a??ing exa?ples ................................................................................................ 11 ? complementary pwm output ..................................................................... 116 over current protection .............................................................................. 118 ocp fun ?iton ....................................................................................................................... 118 ocp ci ??uit ope?ation ......................................................................................................... 118 input voltage range ............................................................................................................. 119 ocp registe ? ....................................................................................................................... 119 offset cali ??ation ................................................................................................................ 1?7 over voltage protection and under voltage protection ........................... 127 ouvp registe ? .................................................................................................................... 1?8 usb charge/discharge auto detection ..................................................... 131 usb0 ................................................................................................................................... 131
rev. 1.30 ? de?e??e? 1?? ?01? rev. 1.30 5 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu usb1? usb? ....................................................................................................................... 13? usb cha?ge/dis?ha? ge auto dete?tion registe?s .............................................................. 133 interrupts ...................................................................................................... 136 inte??upt registe?s ............................................................................................................... 13? inte??upt ope?ation .............................................................................................................. 1?3 exte?nal inte??upt ................................................................................................................. 1?5 uvp inte ??upt ...................................................................................................................... 1?5 ovp inte ??upt ...................................................................................................................... 1?5 ocp inte ??upt ...................................................................................................................... 1?? multi-fun?tion inte??upt ........................................................................................................ 1?? a/d conve?te? inte??upt ....................................................................................................... 1?? ti ?e base inte??upts ........................................................................................................... 1?7 eeprom inte??upt .............................................................................................................. 1?8 lvd inte ??upt ....................................................................................................................... 1?8 tm inte??upts ....................................................................................................................... 1?8 inte?? upt wake-up fun?tion ................................................................................................. 1?8 p?og?a??ing conside?ations .............................................................................................. 1?9 low voltage detector C lvd ....................................................................... 150 lvd registe ? ....................................................................................................................... 150 lvd ope ?ation ..................................................................................................................... 151 scom function for lcd .............................................................................. 152 lcd ope?ation .................................................................................................................... 15? lcd bias cont?ol ................................................................................................................ 153 application circuit ....................................................................................... 154 instruction set .............................................................................................. 155 int?odu?tion ......................................................................................................................... 155 inst?u? tion ti?ing ................................................................................................................ 155 moving and t ?ansfe??ing data ............................................................................................. 155 a?ith?eti? ope?ations .......................................................................................................... 155 logi?al and rotate ope?ation ............................................................................................. 15? b?an?hes and cont? ol t ?ansfe? ........................................................................................... 15? bit ope?ations ..................................................................................................................... 15? ta ?le read ope?ations ....................................................................................................... 15? othe? ope?ations ................................................................................................................. 15? instruction set summary ............................................................................ 157 ta ?le conventions ............................................................................................................... 157 instruction defnition ................................................................................... 159 package information ................................................................................... 168 ? 8-pin ssop (150 ?il) outline di?ensions ........................................................................ 1?9
rev. 1.30 ? de?e??e? 1?? ?01? rev. 1.30 7 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu features cpu features ? operating voltage f sys = 7.5mhz: 2.55v~5.50v f sys = 15mhz: 4.50 v~5.50v ? up to 0.27s instruction cycle with 15 mhz system clock at v dd =5v ? power down and wake-up functions to reduce power consumption ? oscillators internal rc -- hirc internal 32khz -- lirc ? multi-mode operation: normal, slow, idle and sleep ? all instructions executed in one or two instruction cycles ? table read instructions ? 63 powerful instructions ? 8-level subroutine nesting ? bit manipulation instruction peripheral features ? flash program memory: 4k16 ? ram data memory: 1928 ? true eeprom memory: 648 ? watchdog timer function ? up to 26 bidirectional i/o lines ? software controlled 4-scom lines lcd driver with 1/2 bias ? three pin-shared external interrupts ? one 16-bit stm ? three 10-bit ptms ? two complementary pwm output with dead time control ? two over current protection (ocp) with interrupt ? one over/under voltage protection (ouvp) with interrupt ? usb charge/discharge auto detection function ? dual time-base functions for generation of fxed time interrupt signals ? 14-channel 12-bit resolution a/d converter (external input) ? low voltage reset function ? low voltage detect function ? one integrated ldo: 5v output ? ht45fh4n only ? 2 level shift output pins ? ht45fh4n only ? package: 28-pin ssop
rev. 1.30 ? de?e??e? 1?? ?01? rev. 1.30 7 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu device features ht45fh4n ax/bx pin at reset output high cx / dx pin at reset output low inte?nally conne?ted pb4/out0la, pb3/out0hc level shift ax/bx is non-inve? sion output of input a cx / dx is inve? sion output of input c peripheral features table general description 7kh ghylfh lv d )odvk 0hpru wsh elw kljk shuirupdfh 5,6& dufklwhfwxuh plfurfrwuroohu 2iihulj xvhuv wkh fryhlhfh ri )odvk 0hpru pxowlsurjudpplj ihdwxuhv wklv ghylfh dovr lfoxghv d zlgh udjh ri ixfwlrv dg ihdwxuhv 2wkhu phpru lfoxghv d duhd ri 50 dwd 0hpru dv zhoo dv d duhd ri wuxh ((3520 phpru iru vwrudjh ri ryrodwloh gdwd vxfk dv vhuldo xpehuvfdoleudwlrgdwdhwf dorj ihdwxuhv lfoxgh d pxowlfkdho elw fryhuwhu wzr ryhu fxuuhw surwhfwlr ixfwlrv d ryhuxghu yrowdjh surwhfwlr ixfwlr d 86 fkdujhglvfkdujh dxwr ghwhfwlr ixfwlr dg d /2 uhjxodwru 0xowlsoh dg h[wuhpho h[leoh 7lphu 0rgxohv surylgh wlplj sxovh jhhudwlr dg 3:0 jhhudwlr ixfwlrv 3urwhfwlyh ihdwxuhv vxfk dv d lwhudo :dwfkgrj 7lphu /rz 9rowdjh 5hvhw dg /rz 9rowdjh hwhfwru frxsohg zlwk h[fhoohw rlvh lppxlw dg (6 surwhfwlr hvxuh wkdwuholdeohrshudwlrlvpdlwdlhglkrvwlohhohfwulfdohylurphwv ixoo fkrlfh ri +,5& dg /,5& rvfloodwru ixfwlrv duh surylghg lfoxglj d ixoo lwhjudwhg vvwhp rvfloodwru zklfk uhtxluhv r h[whudo frpsrhwv iru lwv lpsohphwdwlr 7kh delolw wr rshudwh dg vzlwfk gdplfdoo ehwzhh d udjh ri rshudwlj prghv xvlj gliihuhw forfn vrxufhv jlyhvxvhuvwkhdelolwwrrswlplvhplfurfrwuroohurshudwlrdgpllpl]hsrzhufrvxpswlr 7klv ghylfh frwdlv 86 sruwv zklfk duh xvhg wr lpsohphw wkh &kdujhlvfkdujh hwhfwlr ixfwlr ovr wkh lfoxvlr ri ioh[leoh ,2 surjudpplj ihdwxuhv 7lphdvh ixfwlrv dorj zlwk pd rwkhu ihdwxuhv hvxuh wkdw wkh ghylfh zloo ilg h[fhoohw xvh l 86 fkdujhglvfkdujh dssolfdwlrv
rev. 1.30 8 de?e??e? 1?? ?01? rev. 1.30 9 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu selection table most features are common to all devices and the main features distinguishing them are the i/o pin count and level shift output pins. the following table summarises the main features of each device. part no. v dd program memory data memory data eeprom i/o ext. interrupt a/d timer module stacks usb ldo level shift output pins package ht?5f?n ?.55v~ 5.5v ?k1? 19? 8 ?? 8 ?? 3 1?- ?it1? 1?-?it stm1 10-?it ptm3 8 3 ?8ssop ht?5fh?n ?.55v~ 5.5v ?k1? 19?8 ?? 8 ?1 3 1?- ?it1? 1?-?it stm1 10-?it ptm3 8 3 ax/bx cx / dx ?8ssop block diagram 8-bit risc mcu core i / o timer modules flash program memory eeprom data memory flash/eeprom programming circuitry ram data memory time base level shift ldo for ht45fh4n only low voltage reset watchdog timer low voltage detect interrupt controller reset circuit internal rc oscillators 12 -bit a/ d converter over current protection over/ under voltage protection usb charge/discharge auto detection
rev. 1.30 8 de?e??e? 1?? ?01? rev. 1.30 9 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu pin assignment                                                   
           
      
 
      
 
                                              

    
       
      
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rev. 1.30 10 de?e??e? 1?? ?01? rev. 1.30 11 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu                                                        
              
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?            ? ?   ?? ?? note: 1. bracketed pin names indicate non-default pinout remapping locations. 2. if the pin-shared pin functions have multiple outputs simultaneously, its pin names at the right side of the / sign can be used for higher priority. 3. both actual mcu and ocds ev devices have the same package type. the ocdsck and ocdsda pins are only available for the ocds ev device. more details are described in the ocds section. 4. for ht45fh4n device the i/o lines, pb4/out0l and pb3/out0h, are internally connected to the level shift inputs, a and c respectively. the i/o lines, pb1/[out0l]/out1l, pb2/[out0h]/out1h and pd1/an9/d0- are not connected to the external pins. the pin 25 and pin 26 must be connected together in the application pcb.
rev. 1.30 10 de?e??e? 1?? ?01? rev. 1.30 11 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu pin descriptions with the exception of the power pins and some relevant transformer control pins, all pins on these devices can be referenced by their port name, e.g. pa0, pa1 etc, which refer to the digital i/o function of the pins. however these port pins are also shared with other function such as the analog to digital converter, timer module pins etc. the function of each pin is listed in the following table, however the details behind how each pin is confgured is contained in other sections of the datasheet. HT45F4N pin name function opt i/t o/t description pa0/tp3_1/an0 pa0 papu pawu st cmos gene?al pu?pose i/o. registe? ena?led pull-up and wake-up. tp3_1 tmpc1 st cmos tm3 i/o an0 adcr0 acerl an adc input pa1/dapwr/an1/ vref pa1 papu pawu st cmos gene?al pu?pose i/o. registe? ena?led pull-up and wake-up. dapwr an d/a conve ?te? powe? input an1 adcr0 acerl an adc input vref adcr1 an a/d conve?te? ?efe?en?e voltage input pa ?/[int0]/tck?/ an? pa ? papu pawu st cmos gene?al pu?pose i/o. registe? ena?led pull-up and wake-up. int0 integ intc1 st exte?nal inte??upt 0 tck? st tm? ?lo?k input an? acerl adcr0 an adc input pa3/[int1]/tck1/ scom? pa3 papu pawu st cmos gene?al pu?pose i/o. registe? ena?led pull-up and wake-up. int1 integ intc1 st exte?nal inte??upt 1 tck1 st tm1 ?lo?k input scom? scomc scom softwa?e ?ont?olled lcd com pa ?/[int?]/tp0_1/ [out1h]/scom1 pa ? papu pawu st cmos gene?al pu?pose i/o. registe? ena?led pull-up and wake-up. int? integ intc1 st exte?nal inte??upt ? tp0_1 tmpc0 st cmos tm0 i/o out1h prm tmpc1 cmos co?ple?enta?y pwm1 output scom1 scomc scom softwa?e ?ont?olled lcd com pa5/int0/tck0/ scom3 pa5 papu pawu st cmos gene?al pu?pose i/o. registe? ena?led pull-up and wake-up. int0 integ intc1 st exte?nal inte??upt 0 tck0 st tm0 ?lo?k input scom3 scomc scom softwa?e ?ont?olled lcd com
rev. 1.30 1? de?e??e? 1?? ?01? rev. 1.30 13 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu pin name function opt i/t o/t description pa ?/int1/tck3/ tp?_1/an3/ icpda/ocdsda pa ? papu pawu st cmos gene?al pu?pose i/o. registe? ena?led pull-up and wake-up. int1 integ intc1 st exte?nal inte??upt 1 tck3 st tm3 ?lo?k input tp?_1 tmpc1 st cmos tm? i/o an3 acerl adcr0 an adc input icpda st cmos in-?i??uit p?og?a??ing data/add?ess pin ocdsda st cmos on-?hip de?ug suppo?t data/add?ess pin? fo? ev ?hip only. pa7/int ?/tp1_1/ an?/icpck/ ocdsck pa7 papu pawu st cmos gene?al pu?pose i/o. registe? ena?led pull-up and wake-up. int? integ intc1 st exte?nal inte??upt ? tp1_1 tmpc0 st cmos tm1 i/o an? acerl adcr0 an adc input icpck st in-?i??uit p?og?a??ing ?lo?k pin ocdsck st on-?hip de?ug suppo?t ?lo?k pin? fo? ev ? hip only. pb0/tp0_0/tp1_0/ tp?_0/tp3_0/ [out1l]/scom0 pb0 pbpu st cmos gene?al pu?pose i/o. registe? ena?led pull-up tp0_0 tmpc0 st cmos tm0 i/o tp1_0 tmpc0 st cmos tm1 i/o tp?_0 tmpc1 st cmos tm? i/o tp3_0 tmpc1 st cmos tm3 i/o out1l prm tmpc1 cmos co?ple?enta?y pwm 1 output scom0 scomc scom softwa?e ?ont?olled lcd com pb1/[out0l]/ out1l pb1 pbpu st cmos gene?al pu?pose i/o. registe? ena?led pull-up out0l prm tmpc0 cmos co?ple?enta?y pwm0 output out1l prm tmpc1 cmos co?ple?enta?y pwm1 output pb?/[out0h]/ out1h pb? pbpu st cmos gene?al pu?pose i/o. registe? ena?led pull-up. out0h prm tmpc0 cmos co?ple?enta?y pwm0 output out1h prm tmpc1 cmos co?ple?enta?y pwm 1 output pb3/out0h pb3 pbpu st cmos gene?al pu?pose i/o. registe? ena?led pull-up. out0h prm tmpc0 cmos co?ple?enta?y pwm0 output pb?/out0l pb? pbpu st cmos gene?al pu?pose i/o. registe? ena?led pull-up. out0l prm tmpc0 cmos co?ple?enta?y pwm0 output pc0/ouvp00/an5 pc0 pcpu st cmos gene?al pu?pose i/o. registe? ena?led pull-up. ouvp00 acerl ouvpc0 an ove?/unde? voltage p?ote?tion input an5 acerl adcr0 an adc input
rev. 1.30 1? de?e??e? 1?? ?01? rev. 1.30 13 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu pin name function opt i/t o/t description pc1/ouvp01/an? pc1 pcpu st cmos gene?al pu?pose i/o. registe? ena?led pull-up. ouvp01 acerl ouvpc0 an ove?/unde? voltage p?ote?tion input an? acerl adcr0 an adc input pc?/ouvp0?/an7 pc? pcpu st cmos gene?al pu?pose i/o. registe? ena?led pull-up. ouvp0? acerl ouvpc0 an ove?/unde? voltage p?ote?tion input an7 acerl adcr0 an adc input pc3/ocp00 pc3 pcpu st cmos gene?al pu?pose i/o. registe? ena?led pull-up. ocp00 ocppc ocp0c0 an ove? ?u??ent p?ote?tion 0 input pc?/ocp01 pc? pcpu st cmos gene?al pu?pose i/o. registe? ena?led pull-up. ocp01 ocppc ocp0c0 an ove? ?u??ent p?ote?tion 0 input pc5/ocp10 pc5 pcpu st cmos gene?al pu?pose i/o. registe? ena?led pull-up. ocp10 ocppc ocp1c0 an ove? ?u??ent p?ote?tion 1 input pc? /ocp11 pc? pcpu st cmos gene?al pu?pose i/o. registe? ena?led pull-up. ocp11 ocppc ocp1c0 an ove? ?u??ent p?ote?tion 1 input pd0/an8/d0+ pd0 pdpu st cmos gene?al pu?pose i/o. registe? ena?led pull-up. an8 acerh adcr0 an adc input d0+ aduc1 an usb d0+ 0.?v output pin pd1/an9/d0- pd1 pdpu st cmos gene?al pu?pose i/o. registe? ena?led pull-up. an9 acerh adcr0 an adc input d0- an usb powe? ?ode dete?tion input pd?/an10/d1+ pd? pdpu st cmos gene?al pu?pose i/o. registe? ena?led pull-up. an10 acerh adcr0 an adc input d1+ aduc1 an usb d1+ dac output pin pd3/an11/d1- pd3 pdpu st cmos gene?al pu?pose i/o. registe? ena?led pull-up. an11 acerh adcr0 an adc input d1- aduc1 an usb d1- dac output pin pd?/an1?/d?+ pd? pdpu st cmos gene?al pu?pose i/o. registe? ena?led pull-up. an1? acerh adcr0 an adc input d?+ aduc1 an usb d?+ dac output pin pd5/an13/d?- pd5 pdpu st cmos gene?al pu?pose i/o. registe? ena?led pull-up. an13 acerh adcr0 an adc input d?- aduc1 an usb d?- dac output pin vdd/avdd/iovdd vdd pwr digital positive powe? supply avdd pwr adc positive powe? supply iovdd pwr i/o po?t positive powe? supply
rev. 1.30 1? de?e??e? 1?? ?01? rev. 1.30 15 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu pin name function opt i/t o/t description vss/avss/iovss vss pwr digital negitive powe? supply avss pwr adc negitive powe? supply iovss pwr i/o po?t negitive powe? supply ht45fh4n pin name function opt i/t o/t description pa0/tp3_1/an0 pa0 papu pawu st cmos gene?al pu?pose i/o. registe? ena?led pull-up and wake-up. tp3_1 tmpc1 st cmos tm3 i/o an0 adcr0 acerl an adc input pa1/dapwr/an1/ vref pa1 papu pawu st cmos gene?al pu?pose i/o. registe? ena?led pull-up and wake-up. dapwr an d/a conve ?te? powe? input an1 adcr0 acerl an adc input vref adcr1 an a/d conve?te? ?efe?en?e voltage input pa ?/[int0]/tck?/ an? pa ? papu pawu st cmos gene?al pu?pose i/o. registe? ena?led pull-up and wake-up. int0 integ intc1 st exte?nal inte??upt 0 tck? st tm? ?lo?k input an? acerl adcr0 an adc input pa3/[int1]/tck1/ scom? pa3 papu pawu st cmos gene?al pu?pose i/o. registe? ena?led pull-up and wake-up. int1 integ intc1 st exte?nal inte??upt 1 tck1 st tm1 ?lo?k input scom? scomc scom softwa?e ?ont?olled lcd com pa ?/[int?]/tp0_1/ [out1h]/scom1 pa ? papu pawu st cmos gene?al pu?pose i/o. registe? ena?led pull-up and wake-up. int? integ intc1 st exte?nal inte??upt ? tp0_1 tmpc0 st cmos tm0 i/o out1h prm tmpc1 cmos co?ple?enta?y pwm1 output scom1 scomc scom softwa?e ?ont?olled lcd com pa5/int0/tck0/ scom3 pa5 papu pawu st cmos gene?al pu?pose i/o. registe? ena?led pull-up and wake-up. int0 integ intc1 st exte?nal inte??upt 0 tck0 st tm0 ?lo?k input scom3 scomc scom softwa?e ?ont?olled lcd com
rev. 1.30 1? de?e??e? 1?? ?01? rev. 1.30 15 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu pin name function opt i/t o/t description pa ?/int1/tck3/ tp?_1/an3/ icpda/ ocdsda pa ? papu pawu st cmos gene?al pu?pose i/o. registe? ena?led pull-up and wake-up. int1 integ intc1 st exte?nal inte??upt 1 tck3 acerl an adc input tp?_1 tmpc1 st cmos tm? i/o an3 acerl adcr0 an adc input icpda st cmos in-?i??uit p?og?a??ing data/add?ess pin ocdsda st cmos on-?hip de?ug suppo?t data/add?ess pin? fo? ev ?hip only. pa7/int ?/tp1_1/ an?/icpck/ ocdsck pa7 papu pawu st cmos gene?al pu?pose i/o. registe? ena?led pull-up and wake-up. int? integ intc1 st exte?nal inte??upt ? tp1_1 tmpc0 st cmos tm1 i/o an? acerl adcr0 an adc input icpck st in-?i??uit p?og?a??ing ?lo?k pin ocdsck st on-?hip de?ug suppo?t ?lo?k pin? fo? ev ? hip only. pb0/tp0_0/tp1_0/ tp?_0/tp3_0/ [out1l]/scom0 pb0 pbpu st cmos gene?al pu?pose i/o. registe? ena?led pull-up tp0_0 tmpc0 st cmos tm0 i/o tp1_0 tmpc0 st cmos tm1 i/o tp?_0 tmpc1 st cmos tm? i/o tp3_0 tmpc1 st cmos tm3 i/o out1l prm tmpc1 cmos co?ple?enta?y pwm 1 output scom0 scomc scom softwa?e ?ont?olled lcd com pc0/ouvp00/an5 pc0 pcpu st cmos gene?al pu?pose i/o. registe? ena?led pull-up. ouvp00 acerl ouvpc0 an ove?/unde? voltage p?ote?tion input an5 acerl adcr0 an adc input pc1/ouvp01/an? pc1 pcpu st cmos gene?al pu?pose i/o. registe? ena?led pull-up. ouvp01 acerl ouvpc0 an ove?/unde? voltage p?ote?tion input an? acerl adcr0 an adc input pc?/ouvp0?/an7 pc? pcpu st cmos gene?al pu?pose i/o. registe? ena?led pull-up. ouvp0? acerl ouvpc0 an ove?/unde? voltage p?ote?tion input an7 acerl adcr0 an adc input pc3/ocp00 pc3 pcpu st cmos gene?al pu?pose i/o. registe? ena?led pull-up. ocp00 ocppc ocp0c0 an ove? ?u??ent p?ote?tion 0 input pc?/ocp01 pc? pcpu st cmos gene?al pu?pose i/o. registe? ena?led pull-up. ocp01 ocppc ocp0c0 an ove? ?u??ent p?ote?tion 0 input
rev. 1.30 1? de?e??e? 1?? ?01? rev. 1.30 17 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu pin name function opt i/t o/t description pc5/ocp10 pc5 pcpu st cmos gene?al pu?pose i/o. registe? ena?led pull-up. ocp10 ocppc ocp1c0 an ove? ?u??ent p?ote?tion 1 input pc? /ocp11 pc? pcpu st cmos gene?al pu?pose i/o. registe? ena?led pull-up. ocp11 ocppc ocp1c0 an ove? ?u??ent p?ote?tion 1 input pd0/an8/d0+ pd0 pdpu st cmos gene?al pu?pose i/o. registe? ena?led pull-up. an8 acerh adcr0 an adc input d0+ aduc1 an usb d0+ 0.?v output pin pd?/an10/d1+ pd? pdpu st cmos gene?al pu?pose i/o. registe? ena?led pull-up. an10 acerh adcr0 an adc input d1+ aduc1 an usb d1+ dac output pin pd3/an11/d1- pd3 pdpu st cmos gene?al pu?pose i/o. registe? ena?led pull-up. an11 acerh adcr0 an adc input d1- aduc1 an usb d1- dac output pin pd?/an1?/d?+ pd? pdpu st cmos gene?al pu?pose i/o. registe? ena?led pull-up. an1? acerh adcr0 an adc input d?+ aduc1 an usb d?+ dac output pin pd5/an13/d?- pd5 pdpu st cmos gene?al pu?pose i/o. registe? ena?led pull-up. an13 acerh adcr0 an adc input d?- aduc1 an usb d?- dac output pin v5 v5 pwr 5v ldo output vcc vcc pwr ldo powe? supply and level shifte? output d?iving supply vdd/avdd/iovdd vdd pwr digital positive powe? supply avdd pwr adc positive powe? supply iovdd pwr i/o po?t positive powe? supply vss/avss/iovss vss pwr digital negitive powe? supply avss pwr adc negitive powe? supply iovss pwr i/o po?t negitive powe? supply ax? bx ax? bx level shift outputs of input a cx ? dx cx ? dx level shift outputs of input c
rev. 1.30 1? de?e??e? 1?? ?01? rev. 1.30 17 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu internal connection description signal name function opt i/t o/t pin-shared mapping pb3 ~ pb? gene?al pu?pose input/output. registe? ena?led pull-up. inte?nally ?onne?ted to the level shift inputs ?espe? tively. pbpu st cmos out0l? out0h pwm output inte?nally ?onne? ted to the level shift inputs a and c tmpc cmos pb?? pb3 a? c level shift inputs. inte?nally ?onne?ted to pb? /out0l and pb3/ out0h ?espe?tively note: i/t: input type; o/t: output type opt: optional by confguration option (co) or register option pwr: power; st: schmitt trigger input cmos: cmos output; an: analog input pin scom: software controlled lcd com level shift input/output relationship and reset condition level shift output level shift input reset state a input = low a input = high ax? bx low high high level shift output level shift input reset state c input = low c input = high cx ? dx high low low absolute maximum ratings supply voltage ................................................................................................ v ss ?0.3v to v ss +6.0v input voltage .................................................................................................. v ss ? 0.3v to v dd +0.3v storage temperature .................................................................................................... -50 ? c to 150?c operating temperature .................................................................................................. -40 ? c to 85 ? c i ol total ................................................................................................................................... 120ma i oh total .................................................................................................................................. - 120ma total power dissipation ......................................................................................................... 500mw note: these are stress ratings only. stresses exceeding the range specified under "absolute maximum ratings" may cause substantial damage to these devices. functional operation of these devices at other conditions beyond those listed in the specifcation is not implied and prolonged exposure to extreme conditions may affect devices reliability.
rev. 1.30 18 de?e??e? 1?? ?01? rev. 1.30 19 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu d.c. characteristics ta = ?5c symbol parameter test conditions min. typ. max. unit v dd conditions v dd ope? ating voltage (hirc) f sys = f hirc /? = 7.5mhz ?.55 5.5 v f sys = f hirc /? = 15mhz ?.5 5.5 ope? ating voltage (lirc) f sys = f lirc = 3?khz ?.55 5.5 i dd ope?ating cu??ent (hirc) 3v f sys =7.5mhz? no load? all pe?iphe? als off ?.? 3.? ?a 5v 5.? 8.1 ?.5v f sys =15mhz? no load? all pe?iphe? als off 5.0 7.5 ?a 5v ?.0 9.0 ope?ating cu??ent (lirc) 3v f sys =3?khz? no load? all pe?iphe? als off ?5 ?5 a 5v ?0 90 i stb stand?y cu??ent (idle0 mode) 3v no load? all pe?iphe? als off 1.9 3.0 a 5v 3.1 5.0 stand?y cu??ent (idle1 mode) 3v f hirc =30mhz? no load? all pe?iphe? als off 1.0 1.5 ?a ?.5v 1.? ?.? 5v 1.8 ?.7 stand?y cu??ent (sleep mode) 3v no load? all pe?iphe? als off 1.8 3.0 a 5v ?.8 5.0 v ih input high voltage (i/o po?ts) 5v 3.5 v dd v 0.8v dd v dd v v il input low voltage (i/o po?ts) 5v 0 1.5 v 0 0.?v dd v v oh output high voltage (pa ? pb0? pc? pd) 3v i oh =-?.??a ?.7 v 5v i oh =-??a ?.5 output high voltage (pb1~pb?) 3v i oh =-1??a ?.7 v 5v i oh =-?0?a ?.5 v ol output low voltage (pa ? pb0? pc? pd) 3v i ol =?.??a 0.3 v 5v i ol =1??a 0.5 output low voltage (pb1~pb?) 3v i ol =1??a 0.3 v 5v i ol =?0?a 0.5 i oh i/o po?t sou??e cu??ent (pa ? pb0? pc? pd) 3v v oh = 0.9v dd -?.? -?.8 ?a 5v -? -1? i/o po?t sou??e cu??ent (pb1~pb?) 3v v oh = 0.9v dd -1? -3? ?a 5v -?0 -80 i ol i/o po?t sink cu??ent (pa ? pb0? pc? pd) 3v v ol = 0.1v dd ?.? 1?.8 ?a 5v 1? 3? i/o po?t sink cu??ent (pb1~pb?) 3v v ol = 0.1v dd 1? 3? ?a 5v ?0 80 i leak input leakage ?u??ent 5v v in =v dd o? v in =v ss 1 a r ph pull-high resistan?e of i/o po?ts 3v ?0 ?0 100 k 5v 10 30 50 k v dr ram data retention voltage 1.0 v i ddp supply cu??ent du?ing p?og?a??ing 10 ?a
rev. 1.30 18 de?e??e? 1?? ?01? rev. 1.30 19 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu a.c. characteristics ta = ?5c symbol parameter test conditions min. typ. max. unit v dd condition f sys syste? c lo?k ?.55v~5.5v f sys = f hirc /? 7.5 mhz ?.5v~5.5v f sys = f hirc /? 15 ?.55v~5.5v f sys = f lirc 3? khz f hirc high speed inte?nal rc os?illato? (hirc) 5v ta = ?5c typ.- ?% 30 typ.+ ?% mhz ?.0v~5.5v ta = -10c to 85c typ.- 5% 30 typ.+ 5% 3.?v~5.5v ta = - ?0c to 85c typ.- 10% 30 typ.+ 10% f lirc low speed inte?nal rc os?illato? (lirc) 5v ta = ?5c typ.- 10% 3? typ.+ 10% khz 5v ta = - ?0c to 85c typ.- 30% 3? typ.+ 30% ?.55v~5.5v ta = - ?0c to 85c typ.- 50% 3? typ.+ ?0% t int exte?nal inte??upt mini?u? pulse width 10 s t tck tm tck input pin mini?u? pulse width 0.3 s t rstd syste? reset delay ti?e (wdt ti ? e-out ha?dwa?e cold reset ) 8.3 1?.7 33.3 ?s t sst syste? s ta?t-up t i?e? p e?iod (f sys = f hirc /?) wake-up f ?o? sleep ?ode o? idle0 ?ode 1? 1/f sys wake-up f ?o? idle1 ?ode ? 1/f sys syste? s ta?t-up t i?e? p e?iod (f sys = f lirc ) wake-up f ?o? idle ?ode o? sleep ?ode ? 1/f sys t sreset mini?u? softwa?e reset width to reset ?5 90 1?0 s t eerd eeprom read ti ?e ? t sys t eewr eeprom w ? ite ti?e ? ? ?s 1rwh 7r pdlqwdlq wkh dffxudf ri wkh lqwhuqdo +?5& rvfloodwru iuhtxhqf d ) ghfrxsolqj fdsdflwru vkrxog eh frqqhfwhgehwzhhq 9''dqg 9??dqgorfdwhgdvforvhwrwkhghylfhdvsrvvleoh
rev. 1.30 ?0 de?e??e? 1?? ?01? rev. 1.30 ?1 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu scom electrical characteristics ta = ?5c symbol parameter test conditions min. typ. max. unit v dd conditions i bias v dd /? bias cu??ent fo? lcd 3v isel[1:0]=00 10.5 15.0 19.5 a 5v 17.5 ?5.0 3?.5 a 3v isel[1:0]=01 ?1 30 39 a 5v 35 50 ?5 a 3v isel[1:0]=10 ?? ?0 78 a 5v 70 100 130 a 3v isel[1:0]=11 8? 1?0 15? a 5v 1?0 ?00 ??0 a v scom v dd /? voltage fo? lcd com po?t ?.55v~ 5.5v no load 0.?75 v dd 0.5 v dd 0.5?5 v dd v lvd & lvr electrical characteristics ta = ?5c symbol parameter test conditions min. typ. max. unit v dd conditions v lvr low voltage reset voltage lvr ena ?le typ.- 5% ?.55 typ.+ 5% v v lvd low voltage dete ?tion voltage lvd ena ?le? sele?ted voltage = ?.7v typ.- 5% ?.7 typ.+ 5% v lvd ena ?le? sele?ted voltage = 3.0v 3.0 lvd ena ?le? sele?ted voltage = 3.3v 3.3 lvd ena ?le? sele?ted voltage = 3.?v 3.? lvd ena ?le? sele?ted voltage = ?.0v ?.0 v bg bandgap refe?en? e voltage typ.- 3% 1.?5 typ.+ 3% v i bg additional cu??ent fo? bandgap refe?en?e ?00 300 a i lvd additional cu??ent fo? lvd ena?le 3v 30 ?5 a 5v ?0 90 t bgs v bg tu ? n on s ta?le t i?e no load ?00 s t lvr mini?u? low voltage width to reset 1?0 ??0 ?80 s t lvd mini?u? low voltage width to inte??upt ?0 1?0 ??0 s t lvds lvdo sta ? le ti?e 5v bandgap is ready ? lvd off : on 15 s
rev. 1.30 ?0 de?e??e? 1?? ?01? rev. 1.30 ?1 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu a/d converter electrical characteristics ta = ?5c symbol parameter test conditions min. typ. max. unit v dd condition v dd a/d conve?te? ope? ating voltage ?.7 5.5 v v adi a/d conve?te? input voltage 0 v ref v v ref a/d conve?te? refe?en? e voltage ? v dd v i adc additional cu??ent fo? a/d conve?te? ena?le 3v no load 0.90 1.35 ?a 5v 1.?0 1.80 dnl diffe ?ential non-linea?ity 5v v ref = v dd ? t adck = 0.5s 1 3 lsb inl integ?al non-linea?ity 5v v ref = v dd ? t adck = 0.5s ? ? lsb t adck a/d conve?te? clo?k pe?iod 0.5 10 s t adc a/d conve?te? conve? sion ti?e (a/d sa? ple and hold ti?e) 1? t adck t ads a/d conve?te? sa? pling ti?e ? t adck t on?st a/d conve?te? o n-to-sta? t ti?e ? s over current circuit electrical characteristics ta = ?5c symbol parameter test conditions min. typ. max. unit v dd condition i ocp ope?ating cu??ent 3v ocpnm[1:0]= 01b o? 10b d/a conve ?te? ?efe?en?e voltage=?.5v 300 500 a 5v ?50 ?00 v os_cmp co?pa?ato? input offset voltage 5v without ?ali??ation? cnof[?:0] =10000b -15 15 ?v with ?ali??ation -? ? ?v v hys hyste?esis 5v ?0 ?0 ?0 ?v v cm_cmp co?pa?ato? co??on mode voltage range 5v v ss v dd - 1.? v v os_opa opa input offset voltage 5v without ?ali??ation? anof[5:0]=100000b -15 15 ?v with ?ali??ation -? ? ?v v cm_opa opa co ?? on mode voltage range 5v -0.? v dd - 1.? v dnl diffe ?ential nonlinea?ity 5v d/a conve ?te? ?efe?en?e voltage=v dd 1 lsb inl integ?al nonlinea?ity 5v d/a conve ?te? ?efe?en?e voltage=v dd ? lsb
rev. 1.30 ?? de?e??e? 1?? ?01? rev. 1.30 ?3 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu over/under voltage circuit electrical characteristics ta = ?5c symbol parameter test conditions min. typ. max. unit v dd condition i ovp ope?ating cu??ent 3v ovpen=1 300 500 a 5v ?50 ?00 i uvp ope?ating cu??ent 3v uvpen=1 300 500 a 5v ?50 ?00 v os input offset voltage 5v -10 10 ?v v hys hyste?esis 5v ?0 ?0 ?0 ?v v cm co?? on mode voltage range 5v v ss v dd - 1.? v dnl diffe ?ential nonlinea?ity 5v d/a conve ?te? ?efe?en?e voltage=v dd 1 lsb inl integ?al nonlinea?ity 5v d/a conve ?te? ?efe?en?e voltage=v dd ? lsb usb charge/discharge detection electrical characteristics ta = ?5c symbol parameter test conditions min. typ. max. unit v dd conditions v dd ope? ating voltage ?.55 5.5 v v dp_src d0+ output voltage d0+ output sou??e ?u??ent at 250a 0.5 0.? 0.7 v v daco d1+? d1-? d?+? d?- output voltage range v ss v ref v v ref dac0? dac1 refe?en?e voltage ?.0 v dd v i dac additional cu??ent fo? dac ena?le 3v no load 0.? 0.9 ?a 5v no load 1.0 1.5 ?a dnl diffe ?ential nonlinea?ity 5v d/a conve ?te? ?efe?en?e voltage=v dd 1 lsb inl integ?al nonlinea?ity 5v d/a conve ?te? ?efe?en?e voltage=v dd ? lsb r o dac0? dac1 r?r output resistan?e 5v 5 k r on analog swit?h on resistan?e ?etween d1+ and d1- 5v d1+ pin input 0.8v ? d1- output ?u??ent 1?a 1?5 ?00 analog swit?h on resistan?e ?etween d?+ and d?- 5v d?+ pin input 0.8v ? d?- output ?u??ent 1?a 1?5 ?00 r pl pull-low resistan?e fo? d0+? d0-? d1+? d1-? d?+. d?- 5v ?00 700 1?00 k err the e??o? fo? d1+? d1-? d?+? d? - output voltage 5v dac ?efe?en?e = v dd ? dac digital value = 1?8? d1+? d1-? d?+ o? d?- ?onne?t 150k to ground ?.57 ?.7 ?.8? v 5v dac ?efe?en?e = v dd ? dac digital value = 110 ? d1+? d1-? d?+ o? d?- ?onne?t 150k to ground 1.9 ?.0 ?.1 v t dp_src v dp_src tu ? n on sta? le ti?e v bg is off ?00 s v bg is on 10 s
rev. 1.30 ?? de?e??e? 1?? ?01? rev. 1.30 ?3 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu ldo regulator electrical characteristics c load =1f, ta = 25c symbol parameter test conditions min. typ. max. unit v dd condition v in input voltage ? ?8 v v out output voltage ta = ?5 c ? i load = 1?a? v in = v out + 1v typ.- ?% 5 typ.+ ?% v -?0 c ta < 85 c ? i load = 1?a? v in = v out + 1v typ.- 5% 5 typ.+ 5% v v load load regulation (note 1) 1? a i load 30?a v in = v out + 1v 0.09 0.18 %/?a v drop d? opout voltage (note ?) v out = ?%? i load = 1?a v in = v out + ?v 100 ?v i q quies?ent cu??ent no load? v in = 1?v ? ? a v line line regulation ?v v in ?8v ? i load = 1?a 0.? %/v tc temperature coeffcient -?0 c ta < 85 c ? v in = v out + 1v ? i load = 10?a 0.9 ? ?v/c note: 1. load regulation is measured at a constant junction temperature, using pulse testing with a low on time and is guaranteed up to the maximum power dissipation. power dissipation is determined by the input/ output differential voltage and the output current. guaranteed maximum power dissipation will not be available over the full input/output range. the maximum allowable power dissipation at any ambient temperature is p d =(t j(max) -ta)/ ja 2. dropout voltage is defned as the input voltage minus the output voltage that produces a 2% change in the output voltage from the value at v in =v out +2v. level converter electrical characteristics ta = ?5c symbol parameter test conditions min. typ. max. unit v dd condition i source output sou??e cu??ent of ax? bx? cx ? dx v cc =1?v ? v oh =10.?v -?0 -90 ?a i sink output sink cu??ent of ax? bx? cx ? dx v cc =1?v ? v ol =1.?v ?0 90 ?a power on reset electrical characteristics ta = ?5c symbol parameter test conditions min. typ. max. unit v dd condition v por v dd sta? t voltage to ensu?e powe?-on reset 100 ?v rr por v dd rising rate to ensu?e powe?-on reset 0.035 v/?s t por mini?u? ti?e fo? v dd stays at v por to ensu?e powe?-on reset 1 ?s
rev. 1.30 ?? de?e??e? 1?? ?01? rev. 1.30 ?5 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu              system architecture a key factor in the high-performance features of the holtek range of microcontrollers is attributed to their internal system architecture. the device takes advantage of the usual features found within risc microcontrollers providing increased speed of operation and periodic performance. the pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. an 8-bit wide alu is used in practically all instruction set operations, which carries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. the internal data path is simplifed by moving data through the accumulator and the alu. certain internal registers are implemented in the data memory and can be directly or indirectly addressed. the simple addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional i/o and a/d control system with maximum reliability and flexibility. this makes the device suitable for low-cost, high-volume production for controller applications. clocking and pipelining the main system clock, derived from either an hirc or lirc oscillator is subdivided into four internally generated non-overlapping clocks, t1~t4. the program counter is incremented at the beginning of the t1 clock during which time a new instruction is fetched. the remaining t2~t4 clocks carry out the decoding and execution functions. in this way, one t1~t4 clock cycle forms one instruction cycle. although the fetching and execution of instructions takes place in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one instruction cycle. the exception to this are instructions where the contents of the program counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute.                                                         
                ?                  ?       ? ? ? ? ? ? system clock and pipelining
rev. 1.30 ?? de?e??e? 1?? ?01? rev. 1.30 ?5 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu for instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. an extra cycle is required as the program takes one cycle to frst obtain the actual jump or call address and then another cycle to actually execute the branch. the requirement for this extra cycle should be taken into account by programmers in timing sensitive applications.                             
      ? ? ? ?     ?  ? ? ?   ?                                  ? instruction fetching program counter during program execution, the program counter is used to keep track of the address of the next instruction to be executed. it is automatically incremented by one each time an instruction is executed except for instructions, such as jmp or call that demand a jump to a non- consecutive program memory address. only the lower 8 bits, known as the program counter low register, are directly addressable by the application program. when executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the required address into the program counter. for conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained. program counter program counter high byte pcl register pc11~pc8 pcl7~pcl0 the lower byte of the program counter, known as the program counter low register or pcl, is available for program control and is a readable and writeable register. by transferring data directly into this register, a short program jump can be executed directly, however, as only this low byte is available for manipulation, the jumps are limited to the present page of memory, that is 256 locations. when such program jumps are executed it should also be noted that a dummy cycle will be inserted. manipulating the pcl register may cause program branching, so an extra cycle is needed to pre-fetch.
rev. 1.30 ?? de?e??e? 1?? ?01? rev. 1.30 ?7 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu stack this is a special part of the memory which is used to save the contents of the program counter only. the stack is neither part of the data nor part of the program space, and is neither readable nor writeable. the activated level is indexed by the stack pointer, and is neither readable nor writeable. at a subroutine call or interrupt acknowledge signal, the contents of the program counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, signaled by a return instruction, ret or reti, the program counter is restored to its previous value from the stack. after a device reset, the stack pointer will point to the top of the stack. if the stack is full and an enabled interrupt takes place, the interrupt request fag will be recorded but the acknowledge signal will be inhibited. when the stack pointer is decremented, by ret or reti, the interrupt will be serviced. this feature prevents stack overfow allowing the programmer to use the structure more easily. however, when the stack is full, a call subroutine instruction can still be executed which will result in a stack overfow. precautions should be taken to avoid such cases which might cause unpredictable program branching. if the stack is overfow, the frst program counter save in the stack will be lost.                                
                            arithmetic and logic unit C alu the arithmetic-logic unit or alu is a critical area of the microcontroller that carries out arithmetic and logic operations of the instruction set. connected to the main microcontroller data bus, the alu receives related instruction codes and performs the required arithmetic or logical operations after which the result will be placed in the specifed register. as these alu calculation or operations may result in carry, borrow or other status changes, the status register will be correspondingly updated to refect these changes. the alu supports the following functions: ? arithmetic operations: add, addm, adc, adcm, sub, subm, sbc, sbcm, daa ? logic operations: and, or, xor, andm, orm, xorm, cpl, cpla ? rotation: rra, rr, rrca, rrc, rla, rl, rlca, rlc ? increment and decrement: inca, inc, deca, dec ? branch decision: jmp, sz, sza, snz, siz, sdz, siza, sdza, call, ret, reti
rev. 1.30 ?? de?e??e? 1?? ?01? rev. 1.30 ?7 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu flash program memory the program memory is the location where the user code or program is stored. for this device the program memory is flash type, which means it can be programmed and re-programmed a large number of times, allowing the user the convenience of code modification on the same device. by using the appropriate programming tools, this flash device offers users the flexibility to conveniently debug and develop their applications while also offering a means of feld programming and updating. structure the program memory has a capacity of 4k16 bits. the program memory is addressed by the program counter and also contains data, table information and interrupt entries. table data, which can be setup in any location within the program memory, is addressed by a separate table pointer register. special vectors within the program memory, certain locations are reserved for the reset and interrupts. the location 000h is reserved for use by the device reset for program initialisation. after a device reset is initiated, the program will jump to this location and begin execution.                               
   
   
 
   
  
   
 
   
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rev. 1.30 ?8 de?e??e? 1?? ?01? rev. 1.30 ?9 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu look-up table any location within the program memory can be defned as a look-up table where programmers can store fxed data. to use the look-up table, the table pointer must frst be setup by placing the address of the look up data to be retrieved in the table pointer register, tblp and tbhp. these registers defne the total address of the look-up table. after setting up the table pointer, the table data can be retrieved from the program memory using the tabrd[m] or tabrdl[m] instructions, respectively. when the instruction is executed, the lower order table byte from the program memory will be transferred to the user defined data memory register [m] as specified in the instruction. the higher order table data byte from the program memory will be transferred to the tblh special register. any unused bits in this transferred higher order byte will be read as 0. the accompanying diagram illustrates the addressing data fow of the look-up table.                           
 
                

             instruction table location bits b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 tabrd [ ?] @11 @10 @9 @8 @7 @? @5 @? @3 @? @1 @0 tabrdl [ ?] 1 1 1 1 @7 @? @5 @? @3 @? @1 @0 table location note: b11~b0: table location bits @7~@0: table pointer (tblp) bits @11~@8: table pointer (tbhp) bits table program example the following example shows how the table pointer and table data is defned and retrieved from the microcontroller. this example uses raw table data located in the program memory which is stored there using the org statement. the value at this org statement is f00h which refers to the start address of the last page within the 4k words program memory of the device. the table pointer is setup here to have an initial value of 06h. this will ensure that the frst data read from the data table will be at the program memory address f06h or 6 locations after the start of the last page. note that the value for the table pointer is referenced to the frst address of the present page if the tabrd [m] instruction is being used. the high byte of the table data which in this case is equal to zero will be transferred to the tblh register automatically when the tabrd [m] instruction is executed . because the tblh register is a read-only register and cannot be restored, care should be taken to ensure its protection if both the main routine and interrupt service routine use table read instructions. if using the table read instructions, the interrupt service routines may change the value of the tblh and subsequently cause errors if used again by the main routine. as a rule it is recommended that simultaneous use of the table read instructions should be avoided. however, in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. note that all table related instructions require two instruction cycles to complete their operation.
rev. 1.30 ?8 de?e??e? 1?? ?01? rev. 1.30 ?9 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu table read program example tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2 : : mov a,06h ; initialise low table pointer - note that this address is referenced mov tblp,a mov a,0fh ; initialise high table pointer mov tbhp,a : : tabrd tempreg1 ; transfers value in table referenced by table pointer data at program ; memory address f06h transferred to tempreg1 and tblh dec tblp ; reduce value of table pointer by one tabrd tempreg2 ; transfers value in table referenced by table pointer data at program ; memory address f05h transferred to tempreg2 and tblh in this ; example the data 1ah is transferred to tempreg1 and data 0fh to ; register tempreg2 : : org f00h ; sets initial address of program memory dc 00ah, 00bh, 00ch, 00dh, 00eh, 00fh, 01ah, 01bh : : in circuit programming the provision of flash type program memory provides the user with a means of convenient and easy upgrades and modifcations to their programs on the same device. as an additional convenience, holtek has provided a means of programming the microcontroller in-circuit using a 4-pin interface. this provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller, and then programming or upgrading the program at a later stage. this enables product manufacturers to easily keep their manufactured products supplied with the latest program releases without removal and re-insertion of the device. the holtek flash mcu to writer programming pin correspondence table is as follows: holtek write pins mcu programming pins function icpda pa ? p?og?a??ing se?ial data/add?ess icpck pa7 p?og?a??ing se?ial clo?k vdd vdd powe? supply vss vss g?ound during the programming process, the user must take care to ensure that no other outputs are connected to these two pins. the program memory and eeprom data memory can both be programmed serially in-circuit using this 4-wire interface. data is downloaded and uploaded serially on a single pin with an additional line for the clock. two additional lines are required for the power supply. the technical details regarding the in-circuit programming of the device are beyond the scope of this document and will be supplied in supplementary literature.
rev. 1.30 30 de?e??e? 1?? ?01? rev. 1.30 31 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu                          
                        note: * may be resistor or capacitor. the resistance of * must be greater than 1k or the capacitance of * must be less than 1nf. on-chip debug support C ocds an ev chip exists for the purposes of device emulation. this ev chip device also provides an on-chip debug function to debug the device during the development process. the ev chip and the actual mcu devices are almost functionally compatible except for the on-chip debug function. users can use the ev chip device to emulate the real chip device behavior by connecting the ocdsda and ocdsck pins to the holtek ht-ide development tools. the ocdsda pin is the ocds data/address input/output pin while the ocdsck pin is the ocds clock input pin. when users use the ev chip for debugging, other functions which are shared with the ocdsda and ocdsck pins in the actual mcu device will have no effect in the ev chip. however, the two ocds pins which are pin-shared with the icp programming pins are still used as the flash memory programming pins for icp. for a more detailed ocds description, refer to the corresponding document named holtek e-link for 8-bit mcu ocds users guide. holtek e-link pins ev chip pins pin description ocdsda ocdsda on-?hip de?ug suppo?t data/add?ess input/output ocdsck ocdsck on-?hip de?ug suppo?t clo?k input vdd vdd powe? supply gnd vss g?ound mcu device ev chip device ht?5f?n ht?5v?n ht?5fh?n ht?5vh?n
rev. 1.30 30 de?e??e? 1?? ?01? rev. 1.30 31 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu ram data memory the data memory is a volatile area of 8-bit wide ram internal memory and is the location where temporary information is stored. structure divided into two sections, the frst of these is an area of ram, known as the special function data memory. here are located registers which are necessary for correct operation of the device. many of these registers can be read from and written to directly under program control, however, some remain protected from user manipulation. the second area of data memory is known as the general purpose data memory, which is reserved for general purpose use. all locations within this area are read and write accessible under program control. 00h 7fh 80h ffh spe?ial pu?pose data me?o?y gene?al pu?pose data me?o?y eec at ?0h in bank 1 bank 0 80h in bank 1 bfh in bank 1 data memory structure the overall data memory is subdivided into two banks. the special purpose data memory registers are accessible in all banks, with the exception of the eec register at address 40h, which is only accessible in bank 1. switching between the different data memory banks is achieved by setting the bank pointer to the correct value. the start address of the data memory for the device is the address 00h.
rev. 1.30 3? de?e??e? 1?? ?01? rev. 1.30 33 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu bank 0 , 1 bank 0 , 1 bank 0 bank1 bank 0 , 1 00h iar0 ?0h adrl ?0h unused eec ?0h ocp0c0 01h mp0 ?1h adrh ?1h unused ?1h ocp0c1 0?h iar1 ??h adcr0 ??h unused ??h ocp0da 03h mp1 ?3h adcr1 ?3h unused ?3h a0cal 0?h bp ??h acerl ??h unused ??h c0cal 05h acc ?5h acerh ?5h unused ?5h ocp1c0 0?h pcl ??h ctrl ??h unused ??h ocp1c1 07h tblp ?7h lvrc ?7h scomc ?7h ocp1da 08h tblh ?8h tm0c0 ?8h prm ?8h a1cal 09h tbhp ?9h tm0c1 ?9h cpr0 ?9h c1cal 0ah status ?ah tm0dl ?ah cpr1 ?ah ocppc 0bh smod ?bh tm0dh ?bh ovpda ?bh aduda0 0ch lvdc ?ch tm0al ?ch uvpda ?ch aduda1 0dh integ ?dh tm0ah ?dh ouvpc0 ?dh aduc0 0eh intc0 ?eh tm0rp ?eh ouvpc1 ?eh aduc1 0fh intc1 ?fh tm1c0 ?fh ouvpc? ?fh aduc? 10h intc? 30h tm1c1 50h tm?c0 70h unused 11h mfi0 31h tm1dl 51h tm?c1 71h unused 1?h mfi1 3?h tm1dh 5?h tm? dl 7?h unused 13h mfi? 33h tm1al 53h tm?dh 73h unused 1?h pa 3?h tm1ah 5?h tm? al 7?h unused 15h pac 35h tm1prl 55h tm?ah 75h unused 1?h papu 3?h tm1prh 5?h tm? prl 7?h unused 17h pawu 37h pc 57h tm?prh 77h unused 18h tmpc1 38h pcc 58h tm3c0 78h unused 19h tmpc0 39h pcpu 59h tm3c1 79h unused 1ah wdtc 3ah pd 5ah tm3dl 7ah unused 1bh tbc 3bh pdc 5bh tm3dh 7bh unused 1ch intc3 3ch pdpu 5ch tm3al 7ch unused 1dh mfi3 3dh pb 5dh tm3ah 7dh unused 1eh eea 3eh pbc 5eh tm3prl 7eh unused 1fh eed 3fh pbpu 5fh tm3prh 7fh unused special purpose data memory structure
rev. 1.30 3? de?e??e? 1?? ?01? rev. 1.30 33 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu special function register description most of the special function register details will be described in the relevant functional section. however, several registers require a separate description in this section. indirect addressing registers C iar0, iar1 the indirect addressing registers, iar0 and iar1, although having their locations in normal ram register space, do not actually physically exist as normal registers. the method of indirect addressing for ram data manipulation uses these indirect addressing registers and memory pointers, in contrast to direct memory addressing, where the actual memory address is specifed. actions on the iar0 and iar1 registers will result in no actual read or write operation to these registers but rather to the memory location specifed by their corresponding memory pointers, mp0 or mp1. acting as a pair, iar0 and mp0 can together access data from bank 0 while the iar1 and mp1 register pair can access data from any bank. as the indirect addressing registers are not physically implemented, reading the indirect addressing registers indirectly will return a result of 00h and writing to the registers indirectly will result in no operation. memory pointers C mp0, mp1 two memory pointers, known as mp0 and mp1 are provided. these memory pointers are physically implemented in the data memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. when any operation to the relevant indirect addressing registers is carried out, the actual address that the microcontroller is directed to is the address specifed by the related memory pointer. mp0, together with indirect addressing register, iar0, are used to access data from bank 0, while mp1 and iar1 are used to access data from all banks according to bp register. direct addressing can only be used with bank 0, all other banks must be addressed indirectly using mp1 and iar1. the following example shows how to clear a section of four data memory locations already defned as locations adres1 to adres4. indirect addressing program example data .section data adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 code org00h start: mov a,04h ; setup size of block mov block,a mov a,offset adres1 ; accumulator loaded with frst ram address mov mp0,a ; setup memory pointer with frst ram address loop: clr iar0 ; clear the data at address defned by mp0 inc mp0 ; increment memory pointer sdz block ; check if last memory location has been cleared jmp loop continue: the important point to note here is that in the example shown above, no reference is made to specifc data memory addresses.
rev. 1.30 3? de?e??e? 1?? ?01? rev. 1.30 35 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu bank pointer C bp for this device, the data memory is divided into two banks, bank0 and bank1. selecting the required data memory area is achieved using the bank pointer. bit 0 of the bank pointer is used to select data memory banks 0~1. the data memory is initialised to bank 0 after a reset, except for a wdt time-out reset in the power down mode, in which case, the data memory bank remains unaffected. it should be noted that the special function data memory is not affected by the bank selection, which means that the special function registers can be accessed from within any bank. directly addressing the data memory will always result in bank 0 being accessed irrespective of the value of the bank pointer. accessing data from bank1 must be implemented using indirect addressing. bp register bit 7 6 5 4 3 2 1 0 na?e dmbp0 r/w r/w por 0 bit 7 ~ 1 unimplemented, read as 0 bit 0 dmbp0 : select data memory banks 0: bank 0 1: bank 1 accumulator C acc the accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the alu. the accumulator is the place where all intermediate results from the alu are stored. without the accumulator it would be necessary to write the result of each calculation or logical operation such as addition, subtraction, shift, etc., to the data memory resulting in higher programming and timing overheads. data transfer operations usually involve the temporary storage function of the accumulator; for example, when transferring data between one user-defined register and another, it is necessary to do this by passing the data through the accumulator as no direct transfer between two registers is permitted. program counter low register C pcl to provide additional program control functions, the low byte of the program counter is made accessible to programmers by locating it within the special purpose area of the data memory. by manipulating this register, direct jumps to other program locations are easily implemented. loading a value directly into this pcl register will cause a jump to the specifed program memory location, however, as the register is only 8-bit wide, only jumps within the current program memory page are permitted. when such operations are used, note that a dummy cycle will be inserted. look-up table registers C tblp, tbhp, tblh these three special function registers are used to control operation of the look-up table which is stored in the program memory. tblp and tbhp are the table pointers and indicate the location where the table data is located. their value must be setup before any table read commands are executed. their value can be changed, for example using the inc or dec instructions, allowing for easy table data pointing and reading. tblh is the location where the high order byte of the table data is stored after a table read data instruction has been executed. note that the lower order table data byte is transferred to a user defned location.
rev. 1.30 3? de?e??e? 1?? ?01? rev. 1.30 35 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu status register C status this 8-bit register contains the zero fag (z), carry fag (c), auxiliary carry fag (ac), overfow fag (ov), power down fag (pdf), and watchdog time-out fag (to). these arithmetic/logical operation and system management fags are used to record the status and operation of the microcontroller. with the exception of the to and pdf fags, bits in the status register can be altered by instructions like most other registers. any data written into the status register will not change the to or pdf fag. in addition, operations related to the status register may give different results due to the different instruction operations. the to fag can be affected only by a system power-up, a wdt time-out or by executing the clr wdt or halt instruction. the pdf fag is affected only by executing the halt or clr wdt instruction or during a system power-up. the z, ov, ac and c fags generally refect the status of the latest operations. ? c is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise c is cleared. c is also affected by a rotate through carry instruction. ? ac is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise ac is cleared. ? z is set if the result of an arithmetic or logical operation is zero; otherwise z is cleared. ? ov is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared. ? pdf is cleared by a system power-up or executing the clr wdt instruction. pdf is set by executing the halt instruction. ? to is cleared by a system power-up or executing the clr wdt or halt instruction. to is set by a wdt time-out. in addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically. if the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it.
rev. 1.30 3? de?e??e? 1?? ?01? rev. 1.30 37 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu status register bit 7 6 5 4 3 2 1 0 na?e to pdf ov z ac c r/w r r r/w r/w r/w r/w por 0 0 unknown bit 7 ~ 6 unimplemented, read as 0 bit 5 to : watchdog time-out fag 0: after power up or executing the clr wdt or halt instruction 1: a watchdog time-out occurred. bit 4 pdf : power down fag 0: after power up or executing the clr wdt instruction 1: by executing the halt instruction bit 3 ov : overfow fag 0: no overfow 1: an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa. bit 2 z : zero fag 0: the result of an arithmetic or logical operation is not zero 1: the result of an arithmetic or logical operation is zero bit 1 ac : auxiliary fag 0: no auxiliary carry 1: an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction bit 0 c : carry fag 0: no carry-out 1: an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation c is also affected by a rotate through carry instruction.
rev. 1.30 3? de?e??e? 1?? ?01? rev. 1.30 37 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu eeprom data memory one of the special features in the device is its internal eeprom data memory. eeprom, which stands for electrically erasable programmable read only memory, is by its nature a non-volatile form of memory, with data retention even when its power supply is removed. by incorporating this kind of data memory, a whole new host of application possibilities are made available to the designer. the availability of eeprom storage allows information such as product identification numbers, calibration values, specifc user data, system setup data or other product information to be stored directly within the product microcontroller. the process of reading and writing data to the eeprom memory has been reduced to a very trivial affair. eeprom data memory structure the eeprom data memory capacity is up to 648 bits. unlike the program memory and ram data memory, the eeprom data memory is not directly mapped and is therefore not directly accessible in the same way as the other types of memory. read and write operations to the eeprom are carried out in single byte operations using an address and data register in bank 0 and a single control register in bank 1. eeprom registers three registers control the overall operation of the internal eeprom data memory. these are the address register, eea, the data register, eed and a single control register, eec. as both the eea and eed registers are located in bank 0, they can be directly accessed in the same way as any other special function register. the eec register however, being located in bank 1, cannot be directly addressed directly and can only be read from or written to indirectly using the mp1 memory pointer and indirect addressing register, iar1. because the eec control register is located at address 40h in bank 1, the mp1 memory pointer must frst be set to the value 40h and the bank pointer register, bp, set to the value, 01h, before any operations on the eec register are executed. eeprom control registers list name bit 7 6 5 4 3 2 1 0 eea d5 d? d3 d? d1 d0 eed d7 d? d5 d? d3 d? d1 d0 eec wren wr rden rd eea register bit 7 6 5 4 3 2 1 0 na?e d5 d? d3 d? d1 d0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7 ~ 6 unimplemented, read as 0 bit 5 ~ 0 data eeprom address data eeprom address bit 5 ~ bit 0
rev. 1.30 38 de?e??e? 1?? ?01? rev. 1.30 39 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu eed register bit 7 6 5 4 3 2 1 0 na?e d7 d? d5 d? d3 d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 ~ 0 data eeprom data data eeprom data bit 7 ~ bit 0 eec register bit 7 6 5 4 3 2 1 0 na?e wren wr rden rd r/w r/w r/w r/w r/w por 0 0 0 0 bit 7 ~ 4 unimplemented, read as 0 bit 3 wren : data eeprom write enable 0: disable 1: enable this is the data eeprom write enable bit which must be set high before data eeprom write operations are carried out. clearing this bit to zero will inhibit data eeprom write operations. bit 2 wr : eeprom write control 0: write cycle has fnished 1: activate a write cycle this is the data eeprom write control bit and when set high by the application program will activate a write cycle. this bit will be automatically reset to zero by the hardware after the write cycle has fnished. setting this bit high will have no effect if the wren has not frst been set high. bit 1 rden : data eeprom read enable 0: disable 1: enable this is the data eeprom read enable bit which must be set high before data eeprom read operations are carried out. clearing this bit to zero will inhibit data eeprom read operations. bit 0 rd : eeprom read control 0: read cycle has fnished 1: activate a read cycle this is the data eeprom read control bit and when set high by the application program will activate a read cycle. this bit will be automatically reset to zero by the hardware after the read cycle has fnished. setting this bit high will have no effect if the rden has not frst been set high. note: the wren, wr, rden and rd can not be set to 1 at the same time in one instruction. the wr and rd can not be set to 1 at the same time.
rev. 1.30 38 de?e??e? 1?? ?01? rev. 1.30 39 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu reading data from the eeprom to read data from the eeprom, the read enable bit, rden, in the eec register must frst be set high to enable the read function. the eeprom address of the data to be read must then be placed in the eea register. if the rd bit in the eec register is now set high, a read cycle will be initiated. setting the rd bit high will not initiate a read operation if the rden bit has not been set. when the read cycle terminates, the rd bit will be automatically cleared to zero, after which the data can be read from the eed register. the data will remain in the eed register until another read or write operation is executed. the application program can poll the rd bit to determine when the data is valid for reading. writing data to the eeprom the eeprom address of the data to be written must frst be placed in the eea register and the data placed in the eed register. to write data to the eeprom, the write enable bit, wren, in the eec register must frst be set high to enable the write function. after this, the wr bit in the eec register must be immediately set high to initiate a write cycle. these two instructions must be executed consecutively. the global interrupt bit emi should also frst be cleared before implementing any write operations, and then set again after the write cycle has started. note that setting the wr bit high will not initiate a write cycle if the wren bit has not been set. as the eeprom write cycle is controlled using an internal timer whose operation is asynchronous to microcontroller system clock, a certain time will elapse before the data will have been written into the eeprom. detecting when the write cycle has fnished can be implemented either by polling the wr bit in the eec register or by using the eeprom interrupt. when the write cycle terminates, the wr bit will be automatically cleared to zero by the microcontroller, informing the user that the data has been written to the eeprom. the application program can therefore poll the wr bit to determine when the write cycle has ended. write protection protection against inadvertent write operation is provided in several ways. after the device is powered-on the write enable bit in the control register will be cleared preventing any write operations. also at power-on the bank pointer, bp, will be reset to zero, which means that data memory bank 0 will be selected. as the eeprom control register is located in bank 1, this adds a further measure of protection against spurious write operations. during normal program operation, ensuring that the write enable bit in the control register is cleared will safeguard against incorrect write operations. eeprom interrupt the eeprom write interrupt is generated when an eeprom write cycle has ended. the eeprom interrupt must frst be enabled by setting the dee bit in the relevant interrupt register. however as the eeprom is contained within a multi-function interrupt, the associated multi-function interrupt enable bit must also be set. when an eeprom write cycle ends, the def request flag and its associated multi-function interrupt request fag will both be set. if the global, eeprom and multi- function interrupts are enabled and the stack is not full, a jump to the associated multi-function interrupt vector will take place. when the interrupt is serviced only the multi-function interrupt fag will be automatically reset, the eeprom interrupt fag must be manually reset by the application program. more details can be obtained in the interrupt section.
rev. 1.30 ?0 de?e??e? 1?? ?01? rev. 1.30 ?1 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu programming considerations care must be taken that data is not inadvertently written to the eeprom. protection can be periodic by ensuring that the write enable bit is normally cleared to zero when not writing. also the bank pointer could be normally cleared to zero as this would inhibit access to bank 1 where the eeprom control register exist. although certainly not necessary, consideration might be given in the application program to the checking of the validity of new write data by a simple read back process. when writing data the wr bit must be set high immediately after the wren bit has been set high, to ensure the write cycle executes correctly. the global interrupt bit emi should also be cleared before a write cycle is executed and then re-enabled after the write cycle starts. note that the device should not enter the idle or sleep mode until the eeprom read or write operation is totally complete, otherwise, the eeprom read or write operation will fail. note that the device should not enter the idle or sleep mode until the eeprom read or write operation is totally complete. otherwise, the eeprom read or write operation will fail. programming examples reading data from the eeprom - polling method mov a, eeprom_adres ; user defned address mov eea, a mov a, 040h ; setup memory pointer mp1 mov mp1, a ; mp1 points to eec register mov a, 01h ; setup bank pointer mov bp, a set iar1.1 ; set rden bit, enable read operations set iar1.0 ; start read cycle - set rd bit back: sz iar1.0 ; check for read cycle end jmp back clr iar1 ; disable eeprom read/write clr bp mov a, eed ; move read data to register mov read_data, a writing data to the eeprom - polling method mov a, eeprom_adres ; user defned address mov eea, a mov a, eeprom_data ; user defned data mov eed, a mov a, 040h ; setup memory pointer mp1 mov mp1, a ; mp1 points to eec register mov a, 01h ; setup bank pointer mov bp, a ; bp points to data memory bank 1 clr emi set iar1.3 ; set wren bit, enable write operations set iar1.2 ; start write cycle - set wr bit C executed immediately ; after set wren bit set emi back: sz iar1.2 ; check for write cycle end jmp back clr iar1 ; disable eeprom read/write clr bp
rev. 1.30 ?0 de?e??e? 1?? ?01? rev. 1.30 ?1 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu oscillator various oscillator options offer the user a wide range of functions according to their various application requirements. the flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. oscillator selections and operation are selected through registers. oscillator overview in addition to being the source of the main system clock the oscillators also provide clock sources for the watchdog timer and time base interrupts. fully integrated internal oscillators, requiring no external components, are provided to form a wide range of both fast and slow system oscillators. the higher frequency oscillators provide higher performance but carry with it the disadvantage of higher power requirements, while the opposite is of course true for the lower frequency oscillators. with the capability of dynamically switching between fast and slow system clock, the device has the fexibility to optimize the performance/power ratio, a feature especially important in power sensitive portable applications. type name freq. inte?nal high speed rc hirc 30mhz inte?nal low speed rc lirc 3?khz oscillator types system clock confgurations there are two methods of generating the system clock, a high speed oscillator and a low speed oscillator. the high speed oscillator is the internal 30mhz rc oscillator. the low speed oscillator is the internal 32khz (lirc) oscillator. selecting whether the low or high speed oscillator is used as the system oscillator is implemented using the hlclk bit and cks2 ~ cks0 bits in the smod register and as the system clock can be dynamically selected. the actual source clock used for the high speed and the low speed oscillators is chosen via registers. the frequency of the slow speed or high speed system clock is also determined using the hlclk bit and cks2 ~ cks0 bits in the smod register. note that two oscillator selections must be made namely one high speed and one low speed system oscillators. it is not possible to choose a no- oscillator selection for either the high or low speed oscillator.              
                             ?   ?  ?   ??  ?  ? ? ? -  system clock confgurations
rev. 1.30 ?? de?e??e? 1?? ?01? rev. 1.30 ?3 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu internal rc oscillator C hirc the internal rc oscillator is a fully integrated system oscillator requiring no external components. the internal rc oscillator has a frequency of 30mhz. device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. note that if this internal system clock option is selected, as it requires no external pins for its operation. internal 32khz oscillator C lirc the internal 32khz system oscillator is the low frequency oscillator. it is a fully integrated rc oscillator with a typical frequency of 32khz at 5v, requiring no external components for its implementation. device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the infuence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. operating modes and system clocks present day applications require that their microcontrollers have high performance but often still demand that they consume as little power as possible, conficting requirements that are especially true in battery powered portable applications. the fast clocks required for high performance will by their nature increase current consumption and of course vice-versa, lower speed clocks reduce current consumption. as holtek has provided this device with both high and low speed clock sources and the means to switch between them dynamically, the user can optimise the operation of their microcontroller to achieve the best performance/power ratio. system clocks the device has many different clock sources for both the cpu and peripheral function operation. by providing the user with a wide range of clock options using confguration options and register programming, a clock system can be confgured to obtain maximum application performance. the main system clock, can come from either a high frequency, f h , or low frequency, f l , source, and is selected using the hlclk bit and cks2~cks0 bits in the smod register. the high speed system clock can be sourced from the hirc oscillator. the low speed system clock source can be sourced from the lirc oscillator. the other choice, which is a divided version of the high speed system oscillator has a range of f h /2~f h /64.
rev. 1.30 ?? de?e??e? 1?? ?01? rev. 1.30 ?3 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu                 
        
               ?    ?       ?   ??   
 ?    ?   -    ?  ? ?      ?    ??    system clock confgurations note: when the system clock source f sys is switched to f l from f h , the high speed oscillation will stop to conserve the power. thus there is no f h ~f h /64 for peripheral circuit to use. system operation modes there are five different modes of operation for the microcontroller, each one with its own special characteristics and which can be chosen according to the specific performance and power requirements of the application. there are two modes allowing normal operation of the microcontroller, the normal mode and slow mode. the remaining three modes, the sleep, idle0 and idle1 mode are used when the microcontroller cpu is switched off to conserve power. operating mode description cpu f sys f s f tbc n ormal ?ode on f h ~f h /?? on on s low ?ode on f l on on ilde0 ?ode off off on on idle1 ?ode off on on on sleep ?ode off off on off
rev. 1.30 ?? de?e??e? 1?? ?01? rev. 1.30 ?5 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu normal mode as the name suggests this is one of the main operating modes where the microcontroller has all of its functions operational and where the system clock is provided by the high speed oscillator. this mode operates allowing the microcontroller to operate normally with a clock source will come from the high speed oscillator, hirc. the high speed oscillator will however frst be divided by a ratio ranging from 1 to 64, the actual ratio being selected by the cks2~cks0 and hlclk bits in the smod register. although a high speed oscillator is used, running the microcontroller at a divided clock ratio reduces the operating current. slow mode this is also a mode where the microcontroller operates normally although now with a slower speed clock source. the clock source used will be from f l . running the microcontroller in this mode allows it to run with much lower operating currents. in the slow mode, the f h is off. sleep mode the sleep mode is entered when an halt instruction is executed and when the idlen bit in the smod register is low. in the sleep mode the cpu will be stopped. however the f s clocks will continue to operate if the lvden is 1 or the watchdog timer function is enabled. idle0 mode the idle0 mode is entered when a halt instruction is executed and when the idlen bit in the smod register is high and the fsyson bit in the ctrl register is low. in the idle0 mode the system oscillator will be inhibited from driving the cpu, the system oscillator will be stopped, the low frequency clock f l will be on. idle1 mode the idle1 mode is entered when a halt instruction is executed and when the idlen bit in the smod register is high and the fsyson bit in the ctrl register is high. in the idle1 mode the system oscillator will be inhibited from driving the cpu, the system oscillator will continue to run, and this system oscillator may be high speed or low speed system oscillator. in the idle1 mode the low frequency clock f l will be on. note: if lvden=1 and the sleep or idle mode is entered, the lvd and bandgap functions will not be disabled, and the f l clock will be forced to open.
rev. 1.30 ?? de?e??e? 1?? ?01? rev. 1.30 ?5 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu control register the smod register is used to control the internal clocks within the device. smod register bit 7 6 5 4 3 2 1 0 na?e cks? cks1 cks0 lto hto idlen hlclk r/w r/w r/w r/w r r r/w r/w por 1 1 0 0 0 1 0 bit 7 ~ 5 cks2 ~ cks0 : the system clock selection when hlclk is 0 000: f l 001: f l 010: f h /64 011: f h /32 100: f h /16 101: f h /8 110: f h /4 111: f h /2 these three bits are used to select which clock is used as the system clock source. in addition to the system clock source, which can be lirc, a divided version of the high speed system oscillator can also be chosen as the system clock source. bit 4 unimplemented, read as 0 bit 3 lto : lirc system osc sst ready fag 0: not ready 1: ready this is the low speed system oscillator sst ready fag which indicates when the low speed system oscillator is stable after power on reset or a wake-up has occurred. the fag will change to a high level after t cycles. bit 2 hto : hirc system osc sst ready fag 0: not ready 1: ready this is the high speed system oscillator sst ready fag which indicates when the high speed system oscillator is stable after a wake-up has occurred. this fag is cleared to 0 by hardware when the device is powered on and then changes to a high level after the high speed system oscillator is stable. herefore this fag will always be read as 1 by the application program after device power-on. the fag will be low when in the sleep or idle 0 mode but after power on reset or a wake-up has occurred, the fag will change to a high level after clock cycles if the hirc oscillator is used. bit 1 idlen : idle mode control 0: disable 1: enable this is the idle mode control bit and determines what happens when the halt instruction is executed. if this bit is high, when a halt instruction is executed the device will enter the idle mode. in the idle1 mode the cpu will stop running but the system clock will continue to keep the peripheral functions operational, if fsyson bit is high. if fsyson bit is low, the cpu and the system clock will all stop in idle0 mode. if the bit is low the device will enter the sleep mode when a halt instruction is executed. bit 0 hlclk : system clock selection 0: f h /2 ~ f h /64 or f l 1: f h this bit is used to select if the f h clock or the f h /2 ~ f h /64 or f l clock is used as the system clock. when the bit is high the f h clock will be selected and if low the f h /2 ~ h /64 or f l clock will be selected. when system clock switches from the f h clock to the l clock and the f h clock will be automatically switched off to conserve power.
rev. 1.30 ?? de?e??e? 1?? ?01? rev. 1.30 ?7 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu ctrl register bit 7 6 5 4 3 2 1 0 na?e fsyson lvrf lrf wrf r/w r/w r/w r/w r/w por 0 0 0 b it 7 : f sys control in idle mode 0: disable 1: enable bit 6~3 unimplemented, read as 0 bit 2 : lvr function reset fag 0: not occur 1: occurred this bit is set high when a specifc low voltage reset situation condition occurs. this bit can only be cleared to zero by the application program. bit 1 : lvrc control register software reset fag 0: not occur 1: occurred this bit is set high if the lvrc register contains any non defned lvr voltage register values. this in effect acts like a software reset function. this bit can only be cleared to zero by the application program. bit 0 : wdt control register software reset fag 0: not occur 1: occurred this bit is set high by the wdt control register software reset and cleared by the application program. note that this bit can only be cleared to zero by the application program.                                      
   

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rev. 1.30 ?? de?e??e? 1?? ?01? rev. 1.30 ?7 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu operating mode switching the device can switch between operating modes dynamically allowing the user to select the best performance/power ratio for the present task in hand. in this way microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications. in simple terms, mode switching between the normal mode and slow mode is executed using the hlclk bit and cks2~cks0 bits in the smod register while mode switching from the normal/slow modes to the sleep/idle modes is executed via the halt instruction. when a halt instruction is executed, whether the device enters the idle mode or the sleep mode is determined by the condition of the idlen bit in the smod register and fsyson in the ctrl register. when the hlclk bit switches to a low level, which implies that clock source is switched from the high speed clock source, f h , to the clock source, f h /2~f h /64 or f l . if the clock is from the f l , the high speed clock source will stop running to conserve power. when this happens it must be noted that the f h /16 and f h /64 internal clock sources will also stop running, which may affect the operation of other internal functions such as the tms. the accompanying flowchart shows what happens when the device moves between the various operating modes. normal mode to slow mode switching when running in the normal mode, which uses the high speed system oscillator, and therefore consumes more power, the system clock can switch to run in the slow mode by setting the hlclk bit to 0 and setting the cks2~cks0 bits to 000 or 001 in the smod register. this will then use the low speed system oscillator which will consume less power. users may decide to do this for certain operations which do not require high performance and can subsequently reduce power consumption. the slow mode is sourced from the lirc oscillator and therefore requires this oscillator to be stable before full mode switching occurs. this is monitored using the lto bit in the smod register.                           
                    ?         ? ? ?? ? ?    ?? ?      ? ? -      ? ? ?? ? ?     ?? ?      ? ? -      ? ? ?? ? ?    ?? ? 
rev. 1.30 ?8 de?e??e? 1?? ?01? rev. 1.30 ?9 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu slow mode to normal mode switching in slow mode the system uses lirc low speed system oscillator. to switch back to the normal mode, where the high speed system oscillator is used, the hlclk bit should be set to 1 or hlclk bit is 0, but cks2~cks0 is set to 010, 011, 100, 101, 110 or 111. as a certain amount of time will be required for the high frequency clock to stabilise, the status of the hto bit is checked. the amount of time required for high speed system oscillator stabilization depends upon which high speed system oscillator type is used.                        
                         ?         ? ? ?? ? ?   ? ? ??       ? -      ? ? ?? ? ?   ? ? ??       ? -      ? ? ?? ? ?   ? ? ?? 
rev. 1.30 ?8 de?e??e? 1?? ?01? rev. 1.30 ?9 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu entering the sleep mode there is only one way for the device to enter the sleep mode and that is to execute the halt instruction in the application program with the idlen bit in smod register equal to 0 and the wdt or lvd on. when this instruction is executed under the conditions described above, the following will occur: ? the system clock and time base clock will be stopped and the application program will stop at the halt instruction, but the wdt or lvd will remain with the clock source coming from the f l clock. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag, pdf, will be set and the watchdog time-out fag, to, will be cleared. entering the idle0 mode there is only one way for the device to enter the idle0 mode and that is to execute the halt instruction in the application program with the idlen bit in smod register equal to 1 and the fsyson bit in ctrl register equal to 0. when this instruction is executed under the conditions described above, the following will occur: ? the system clock will be stopped and the application program will stop at the halt instruc - tion, but the time base clock f tbc and the low frequency f l clock will be on. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag, pdf, will be set and the watchdog time-out fag, to, will be cleared. entering the idle1 mode there is only one way for the device to enter the idle1 mode and that is to execute the halt instruction in the application program with the idlen bit in smod register equal to 1 and the fsyson bit in ctrl register equal to 1. when this instruction is executed under the conditions described above, the following will occur: ? the system clock and time base clock and f tbc and the low frequency f l will be on and the appli - cation program will stop at the halt instruction. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting . ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag, pdf, will be set and the watchdog time-out fag, to, will be cleared.
rev. 1.30 50 de?e??e? 1?? ?01? rev. 1.30 51 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu standby current considerations as the main reason for entering the sleep or idle mode is to keep the current consumption of the device to as low a value as possible, perhaps only in the order of several micro-amps except in the idle1 mode, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimised. special attention must be made to the i/o pins on the device. all high-impedance input pins must be connected to either a fxed high or low level as any floating input pins could create internal oscillations and result in increased current consumption. this also applies to devices which have different package types, as there may be unbonbed pins. these must either be setup as outputs or if setup as inputs must have pull-high resistors connected. care must also be taken with the loads, which are connected to i/o pins, which are setup as outputs. these should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other cmos inputs. in the idle1 mode the system oscillator is on, if the system oscillator is from the high speed system oscillator, the additional standby current will also be perhaps in the order of several hundred micro-amps. wake-up after the system enters the sleep or idle mode, it can be woken up from one of various sources listed as follows: ? an external falling edge on port a ? a system interrupt ? a wdt overfow if the device is woken up by a wdt overfow, a watchdog timer reset will be initiated. the actual source of the wake-up can be determined by examining the to and pdf flags. the pdf flag is cleared by a system power-up or executing the clear watchdog timer instructions and is set when executing the halt instruction. the to fag is set if a wdt time-out occurs, and causes a wake- up that only resets the program counter and stack pointer, the other fags remain in their original status. each pin on port a can be setup using the pawu register to permit a negative transition on the pin to wake-up the system. when a port a pin wake-up occurs, the program will resume execution at the instruction following the halt instruction. if the system is woken up by an interrupt, then two possible situations may occur. the frst is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the halt instruction. in this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is fnally enabled or when a stack level becomes free. the other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. if an interrupt request flag is set high before entering the sleep or idle mode, the wake-up function of the related interrupt will be disabled.
rev. 1.30 50 de?e??e? 1?? ?01? rev. 1.30 51 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu watchdog timer the watchdog timer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. watchdog timer clock source the watchdog timer clock source is provided by the internal f l clock which is in turn supplied by the lirc oscillator. the watchdog timer source clock is then subdivided by a ratio of 2 8 to 2 18 to give longer timeouts, the actual value being chosen using the ws2~ws0 bits in the wdtc register. the lirc internal oscillator has an approximate period of 32khz at a supply voltage of 5v. however, it should be noted that this specifed internal clock period can vary with v dd , temperature and process variations. watchdog timer control register a single register, wdtc, controls the required timeout period as well as the enable/disable operation. the wdtc register is initiated to 01010011b at any reset but keeps unchanged at the wdt time-out occurrence in a power down state. wdtc register bit 7 6 5 4 3 2 1 0 na?e we? we3 we? we1 we0 ws? ws1 ws0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 1 0 1 0 0 1 1 bit 7~ 3 : wdt enable bit 10101 or 01010: enabled other: reset mcu if these bits are changed due to adverse environmental conditions, the microcontroller will be reset. the reset operation will be activated after 2~3 lirc clock cycles and the wrf bit in the ctrl register will be set high. bit 2~ 0 : select wdt timeout period 000: 2 8 /f s 001: 2 10 /f s 010: 2 12 /f s 011: 2 14 /f s 100: 2 15 /f s 101: 2 16 /f s 110: 2 17 /f s 111: 2 18 /f s these three bits determine the division ratio of the watchdog timer source clock, which in turn determines the timeout period.
rev. 1.30 5? de?e??e? 1?? ?01? rev. 1.30 53 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu ctrl register bit 7 6 5 4 3 2 1 0 na?e fsyson lvrf lrf wrf r/w r/w r/w r/w r/w por 0 0 0 b it 7 : f sys control idle mode describe elsewhere bit 6~ 3 unimplemented, read as 0 bit 2 : lvr function reset fag describe elsewhere bit 1 : lvr control register software reset fag describe elsewhere bit 0 : wdt control register software reset fag 0: not occur 1: occurred this bit is set high by the wdt control register software reset and cleared by the application program. note that this bit can only be cleared to zero by the application program. watchdog timer operation the watchdog timer operates by providing a device reset when its timer overfows. this means that in the application program and during normal operation the user has to strategically clear the watchdog timer before it overfows to prevent the watchdog timer from executing a reset. this is done using the clear watchdog instructions. if the program malfunctions for whatever reason, jumps to an unknown location, or enters an endless loop, these clear instructions will not be executed in the correct manner, in which case the watchdog timer will overfow and reset the device. there are fve bits, we4~we0, in the wdtc register to offer enable and reset control of the watchdog timer. when the we4~we0 bits value are equal to 01010b or 10101b, the wdt function is enabled. however, if the we4~we0 bits are changed to any other values except 01010b and 10101b, which could be caused by adverse environmental conditions such as noise, it will reset the microcontroller after 2~3 lirc clock cycles. after power on these bits will have a value of 01010b. we4 ~ we0 bits wdt function 01010b o? 10101b ena?le any othe? value reset mcu watchdog timer enable/disable control under normal program operation, a watchdog timer time-out will initialise a device reset and set the status bit to. however, if the system is in the sleep or idle mode, when a watchdog timer time-out occurs, the to bit in the status register will be set and only the program counter and stack pointer will be reset. three methods can be adopted to clear the contents of the watchdog timer. the frst is a wdt reset, which means a certain value is written into the we4~we0 bit fled except 01010b and 10101b, t he second is using the watchdog timer software clear instructions and the third is via a halt instruction. there is only one method of using software instruction to clear the watchdog timer. that is to use the single clr wdt instruction to clear the wdt. the maximum time-out period is when the 2 18 division ratio is selected. as an example, with a 32 khz lirc oscillator as its source clock, this will give a maximum watchdog period of around 8 seconds for the 2 18 division ratio, and a minimum timeout of 7.8ms for the 2 8 division ration.
rev. 1.30 5? de?e??e? 1?? ?01? rev. 1.30 53 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu clr wdt inst?u?tion 8 - stage divide? wdt p?es?ale? we ? ~ we 0 ?its wdtc registe? reset mcu f s / ? 8 8 -to -1 mux clr ws ? ~ ws 0 (f s / ? 8 ~ f s / ? 18 ) wdt ti?e -out (? 8 / f s ~ ? 18 / f s ) lirc halt inst?u?tion f s watchdog timer reset and initialisation a reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. the most important reset condition is after power is frst applied to the microcontroller. in this case, internal circuitry will ensure that the microcontroller, after a short delay, will be in a well defined state and ready to execute the frst program instruction. after this power-on reset, certain important internal registers will be set to defned states before the program commences. one of these registers is the program counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest program memory address. another type of reset is when the watchdog timer overflows and resets the microcontroller. all types of reset operations result in different register conditions being setup. another reset exists in the form of a low voltage reset, lvr, where a full reset is implemented in situations where the power supply voltage falls below a certain threshold. reset functions there are four ways in which a microcontroller reset can occur, through events occurring internally: ? power-on reset the most fundamental and unavoidable reset is the one that occurs after power is frst applied to the microcontroller. as well as ensuring that the program memory begins execution from the frst memory address, a power-on reset also ensures that certain other registers are preset to known conditions. all the i/o port and port control registers will power up in a high condition ensuring that all pins will be frst set to inputs. vdd powe? - on reset sst ti?e - out t rstd note: t rstd is power-on delay, typical time=16.7ms power-on reset timing chart
rev. 1.30 5? de?e??e? 1?? ?01? rev. 1.30 55 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu ? low voltage reset C lvr the microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device . the lvr function is always enabled with a specifc lvr voltage, v lvr . if the supply voltage of the device drops to within a range of 0.9v~ v lvr such as might occur when changing the battery, the lvr will automatically reset the device internally and the lvrf bit in the ctrl register will also be set high . f or a valid lvr signal, a low voltage, i.e., a voltage in the range between 0.9v~ v lvr must exist for greater than the value t lvr specifed in the lvd&lvr characteristics. if the low voltage state does not exceed this value , the lvr will ignore the low supply voltage and will not perform a reset function. the actual v lvr is fxed at a value of 2.55v. however, the lvs7~lvs0 bits still have effects on the lvr function. if the lvs7~lvs0 bits are changed to any other value except some certain values defned in the lvrc register by the environmental noise, the lvr will reset the device after 2~3 lirc clock cycles. when this happens, the lrf bit in the ctrl register will be set high . after power on the register will have the value of 01010101b. note that the lvr function will be automatically disabled when the device enters the power down mode.                 note:t rstd is power-on delay, typical time=16.7ms low voltage reset timing chart ? lvrc register bit 7 6 5 4 3 2 1 0 na?e lvs7 lvs ? lvs5 lvs ? lvs3 lvs ? lvs1 lvs0 r/w r/w r/w r/w r/w r r r/w r/w por 0 1 0 1 0 1 0 1 bit 7 ~ 0 : lvr voltage select control 01010101: 2.55v 00110011: 2.55v 10011001: 2.55v 10101010: 2.55v any other value: generates mcu reset C register is reset to por value when an actual low voltage condition occurs, an mcu reset will be generated. the reset operation will be activated after 2~3 lirc clock cycles. in this situation this register contents will remain the same after such a reset occurs. any register value, other than the defined value above, will also result in the generation of an mcu reset. the reset operation will be activated after 2~3 lirc clock cycles. however in this situation this register contents will be reset to the por value.
rev. 1.30 5? de?e??e? 1?? ?01? rev. 1.30 55 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu ? ctrl register bit 7 6 5 4 3 2 1 0 na?e fsyson lvrf lrf wrf r/w r/w r/w r/w r/w por 0 0 0 b it 7 : f sys control idle mode describe elsewhere bit 6~ 3 unimplemented, read as 0 bit 2 : lvr function reset fag 0: not occur 1: occurred this bit is set high when a specifc low voltage reset situation condition occurs. this bit can only be cleared to zero by the application program. bit 1 : lvr control register software reset fag 0: not occur 1: occurred this bit is set high if the lvrc register contains any non defned lvr voltage register values. this in effect acts like a software reset function. this bit can only be cleared to zero by the application program. bit 0 : wdt control register software reset fag describe elsewhere ? watchdog time-out reset during normal operation the watchdog time-out reset during normal operation is the same as a lvr reset except that the watchdog time-out fag to will be set high.                     note: t rstd is power-on delay, typical time=16.7ms wdt time-out reset during normal operation timing chart ? watchdog time-out reset during sleep or idle mode the watchdog time-out reset during sleep or idle mode is a little different from other kinds of reset. most of the conditions remain unchanged except that the program counter and the stack pointer will be cleared to zero and the to fag will be set high . refer to the a.c. characteristics for t sst details.                wdt time-out reset during sleep or idle timing chart
rev. 1.30 5? de?e??e? 1?? ?01? rev. 1.30 57 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu reset initial conditions the different types of reset described affect the reset fags in different ways. these fags, known as pdf and to are located in the status register and are controlled by various microcontroller operations, such as the sleep or idle mode function or watchdog timer. the reset flags are shown in the table: to pdf reset conditions 0 0 powe?-on ?eset u u lvr ?eset du? ing normal o? slow mode ope?ation 1 u wdt ti ?e-out ?eset du? ing normal o? slow mode ope?ation 1 1 wdt ti ?e-out ?eset du?ing idle o? sleep mode ope?ation note: u stands fo? un?hanged the following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. item condition after reset p?og?a? counte? reset to ze?o inte??upts all inte??upts will ?e disa?led wdt clea? afte? ?eset? wdt ?egins ?ounting ti ?e? modules ti ?e? modules will ?e tu? ned off input/output po?ts i/o po?ts will ? e setup as inputs and an0~an13 as a/d input pins sta?k pointe? sta?k pointe? will point to the top of the sta?k the different kinds of resets all affect the internal registers of the microcontroller in different ways. to ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. the following table describes how each type of reset affects each of the microcontroller internal registers. register reset (power on) wdt time-out (normal operation) lvr reset wdt time-out (sleep/idle) mp0 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu mp1 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu bp ---- ---0 ---- ---0 ---- ---0 ---- ---u acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu pcl 0000 0000 0000 0000 0000 0000 0000 0000 tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu tblh xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu tbhp ---- xxxx ---- uuuu ---- uuuu ---- uuuu status --00 xxxx --1u uuuu --uu uuuu --11 uuuu smod 110- 0010 110- 0010 110- 0010 uuu- uuuu lvdc --00 -000 --00 -000 --00 -000 --uu -uuu integ --00 0000 --00 0000 --00 0000 --uu uuuu intc0 -000 0000 -000 0000 -000 0000 -uuu uuuu intc1 0000 0000 0000 0000 0000 0000 uuuu uuuu intc? 0000 0000 0000 0000 0000 0000 uuuu uuuu intc3 0000 0000 0000 0000 0000 0000 uuuu uuuu mfi0 -000 -000 -000 -000 -000 -000 -uuu -uuu mfi1 --00 --00 --00 --00 --00 --00 --uu --uu mfi? --00 --00 --00 --00 --00 --00 --uu --uu mfi3 --00 --00 --00 --00 --00 --00 --uu --uu pa 1111 1111 1111 1111 1111 1111 uuuu uuuu pac 1111 1111 1111 1111 1111 1111 uuuu uuuu
rev. 1.30 5? de?e??e? 1?? ?01? rev. 1.30 57 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu register reset (power on) wdt time-out (normal operation) lvr reset wdt time-out (sleep/idle) papu 0000 0000 0000 0000 0000 0000 uuuu uuuu pawu 0000 0000 0000 0000 0000 0000 uuuu uuuu pb ---1 1111 ---1 1111 ---1 1111 ---u uuuu pbc ---1 1111 ---1 1111 ---1 1111 ---u uuuu pbpu ---0 0000 ---0 0000 ---0 0000 ---u uuuu pc -111 1111 -111 1111 -111 1111 -uuu uuuu pcc -111 1111 -111 1111 -111 1111 -uuu uuuu pcpu -000 0000 -000 0000 -000 0000 -uuu uuuu pd --11 1111 --11 1111 --11 1111 --uu uuuu pdc --11 1111 --11 1111 --11 1111 --uu uuuu pdpu --00 0000 --00 0000 --00 0000 --uu uuuu tmpc0 1100 0000 1100 0000 1100 0000 uuuu uuuu tmpc1 1100 0000 1100 0000 1100 0000 uuuu uuuu wdtc 0101 0011 0101 0011 0101 0011 uuuu uuuu tbc 0011 -111 0011 -111 0011 -111 uuuu -uuu eea --00 0000 --00 0000 --00 0000 --uu uuuu eed 0000 0000 0000 0000 0000 0000 uuuu uuuu eec ---- 0000 ---- 0000 ---- 0000 ---- uuuu adrl (adrfs=0) xxxx ---- xxxx ---- xxxx ---- uuuu ---- adrl (adrfs=1) xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu adrh (adrfs=0) xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu adrh (adrfs=1) ---- xxxx ---- xxxx ---- xxxx ---- uuuu adcr0 0110 0000 0110 0000 0110 0000 uuuu uuuu adcr1 00-0 -000 00-0 -000 00-0 -000 uu-u -uuu acerl 1111 1111 1111 1111 1111 1111 uuuu uuuu acerh --11 1111 --11 1111 --11 1111 --uu uuuu ctrl 0--- -x00 0--- -000 0--- -000 u--- -uuu lvrc 0101 0101 0101 0101 0101 0101 uuuu uuuu tm0c0 0000 0--- 0000 0--- 0000 0--- uuuu u--- tm0c1 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0dl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0dh 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0al 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0ah 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0rp 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1c0 0000 0--- 0000 0--- 0000 0--- uuuu u--- tm1c1 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1dl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1dh ---- --00 ---- --00 ---- --00 ---- --uu tm1al 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1ah ---- --00 ---- --00 ---- --00 ---- --uu tm1rpl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1rph ---- --00 ---- --00 ---- --00 ---- --uu tm?c0 0000 0--- 0000 0--- 0000 0--- uuuu u---
rev. 1.30 58 de?e??e? 1?? ?01? rev. 1.30 59 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu register reset (power on) wdt time-out (normal operation) lvr reset wdt time-out (sleep/idle) tm?c1 0000 0000 0000 0000 0000 0000 uuuu uuuu tm?dl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm?dh ---- --00 ---- --00 ---- --00 ---- --uu tm?al 0000 0000 0000 0000 0000 0000 uuuu uuuu tm?ah ---- --00 ---- --00 ---- --00 ---- --uu tm?rpl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm?rph ---- --00 ---- --00 ---- --00 ---- --uu tm3c0 0000 0--- 0000 0--- 0000 0--- uuuu u--- tm3c1 0000 0000 0000 0000 0000 0000 uuuu uuuu tm3dl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm3dh ---- --00 ---- --00 ---- --00 ---- --uu tm3al 0000 0000 0000 0000 0000 0000 uuuu uuuu tm3ah ---- --00 ---- --00 ---- --00 ---- --uu tm3rpl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm3rph ---- --00 ---- --00 ---- --00 ---- --uu cpr0 ---0 0000 ---0 0000 ---0 0000 ---u uuuu cpr1 ---0 0000 ---0 0000 ---0 0000 ---u uuuu scomc 0000 0000 0000 0000 0000 0000 uuuu uuuu prm -000 0000 -000 0000 -000 0000 -uuu uuuu ovpda 0000 0000 0000 0000 0000 0000 uuuu uuuu uvpda 0000 0000 0000 0000 0000 0000 uuuu uuuu ouvpc0 x000 -000 x000 -000 x000 -000 uuuu -uuu ouvpc1 x000 --00 x000 --00 x000 --00 uuuu --uu ouvpc? 0000 0000 0000 0000 0000 0000 uuuu uuuu ocp0c0 0000 0000 0000 0000 0000 0000 uuuu uuuu ocp0c1 x000 0000 x000 0000 x000 0000 uuuu uuuu ocp0da 0000 0000 0000 0000 0000 0000 uuuu uuuu a0cal 0010 0000 0010 0000 0010 0000 uuuu uuuu c0cal x001 0000 x001 0000 x001 0000 uuuu uuuu ocp1c0 0000 0000 0000 0000 0000 0000 uuuu uuuu ocp1c1 x000 0000 x000 0000 x000 0000 uuuu uuuu ocp1da 0000 0000 0000 0000 0000 0000 uuuu uuuu a1cal 0010 0000 0010 0000 0010 0000 uuuu uuuu c1cal x001 0000 x001 0000 x001 0000 uuuu uuuu ocppc --00 1111 --00 1111 --00 1111 --uu uuuu aduda0 0000 0000 0000 0000 0000 0000 uuuu uuuu aduda1 0000 0000 0000 0000 0000 0000 uuuu uuuu aduc0 -000 0000 -000 0000 -000 0000 -uuu uuuu aduc1 --00 00-0 --00 00-0 --00 00-0 --uu uu-u aduc? --00 0000 --00 0000 --00 0000 --uu uuuu note: "-" not implement "u" stands for "unchanged" "x" stands for "unknown"
rev. 1.30 58 de?e??e? 1?? ?01? rev. 1.30 59 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu input/output ports holtek microcontrollers offer considerable fexibility on their i/o ports. with the input or output designation of every pin fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is provided with an i/o structure to meet the needs of a wide range of application possibilities. the device provides bidirectional input/output lines labeled with port names pa~pd. these i/o ports are mapped to the ram data memory with specifc addresses as shown in the special purpose data memory table. all of these i/o ports can be used for input and output operations. for input operation, these ports are non-latching, which means the inputs must be ready at the t2 rising edge of instruction mov a, [m], where m denotes the port address. for output operation, all the data is latched and remains unchanged until the output latch is rewritten. register name bit 7 6 5 4 3 2 1 0 pa d7 d? d5 d? d3 d? d1 d0 pac d7 d? d5 d? d3 d? d1 d0 papu d7 d? d5 d? d3 d? d1 d0 pawu d7 d? d5 d? d3 d? d1 d0 pb d? d3 d? d1 d0 pbc d? d3 d? d1 d0 pbpu d? d3 d? d1 d0 pc d? d5 d? d3 d? d1 d0 pcc d? d5 d? d3 d? d1 d0 pcpu d? d5 d? d3 d? d1 d0 pd d5 d? d3 d? d1 d0 pdc d5 d? d3 d? d1 d0 pdpu d5 d? d3 d? d1 d0 note: the i/o lines, pb1~pb4 and pd1, are not connected to the external pins for the ht45fh4n device. pull-high resistors many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor. to eliminate the need for these external resistors, all i/o pins, when confgured as an input have the capability of being connected to an internal pull-high resistor. these pull-high resistors are selected using registers papu~pdpu, and are implemented using weak pmos transistors. papu register bit 7 6 5 4 3 2 1 0 na?e d7 d? d5 d? d3 d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 ~ 0 i/o port a bit7~ bit 0 pull-high control 0: disable 1: enable
rev. 1.30 ?0 de?e??e? 1?? ?01? rev. 1.30 ?1 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu pbpu register bit 7 6 5 4 3 2 1 0 na?e d? d3 d? d1 d0 r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 bit 7 ~ 5 unimplemented, read as 0 bit 4 ~ 0 i/o port b bit 4~ bit 0 pull-high control 0: disable 1: enable pcpu register bit 7 6 5 4 3 2 1 0 na?e d? d5 d? d3 d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 unimplemented, read as "0" bit 6 ~ 0 i/o port b bit6~ bit 0 pull-high control 0: disable 1: enable pdpu register bit 7 6 5 4 3 2 1 0 na?e d5 d? d3 d? d1 d0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5~0 i/o port b bit5~ bit 0 pull-high control 0: disable 1: enable port a wake-up the halt instruction forces the microcontroller into the sleep or idle mode which preserves power, a feature that is important for battery and other low-power applications. various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the port a pins from high to low. this function is especially suitable for applications that can be woken up via external switches. each pin on port a can be selected individually to have this wake-up feature using the pawu register. pawu register bit 7 6 5 4 3 2 1 0 na?e d7 d? d5 d? d3 d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 ~ 0 i/o port a bit 7 ~ bit 0 wake up control 0: disable 1: enable
rev. 1.30 ?0 de?e??e? 1?? ?01? rev. 1.30 ?1 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu i/o port control registers each i/o port has its own control register known as pac~pdc, to control the input/output configuration. with this control register, each cmos output or input can be reconfigured dynamically under software control. each pin of the i/o ports is directly mapped to a bit in its associated port control register. for the i/o pin to function as an input, the corresponding bit of the control register must be written as a 1. this will then allow the logic state of the input pin to be directly read by instructions. when the corresponding bit of the control register is written as a 0, the i/o pin will be setup as a cmos output. if the pin is currently setup as an output, instructions can still be used to read the output register. however, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. pac register bit 7 6 5 4 3 2 1 0 na?e d7 d? d5 d? d3 d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 bit 7 ~ 0 i/o port a bit 7 ~ bit 0 input/output control 0: output 1: input pbc register bit 7 6 5 4 3 2 1 0 na?e d? d3 d? d1 d0 r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 bit 7~5 unimplemented, read as 0 bit 4~0 i/o port b bit 4~bit 0 input/output control 0: output 1: input pcc register bit 7 6 5 4 3 2 1 0 na?e d? d5 d? d3 d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 bit 7 unimplemented, read as 0 bit 6~0 i/o port c bit 6~bit 0 input/output control 0: output 1: input
rev. 1.30 ?? de?e??e? 1?? ?01? rev. 1.30 ?3 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu pdc register bit 7 6 5 4 3 2 1 0 na?e d5 d? d3 d? d1 d0 r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 bit 7~6 unimplemented, read as 0 bit 5~0 i/o port d bit 5~bit 0 input/output control 0: output 1: input as the pb1, pb2 and pd1 are not connected to the external pins, it is recommended to set these pins as i/o output high or output low via the related i/o port control bits. pin-remapping functions the fexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions, many of these difficulties can be overcome. the way in which the pin function of each pin is selected is different for each function and a priority order is established where more than one pin function is selected simultaneously. additionally there is a prm register to establish certain pin functions. generally speaking, the analog function has higher priority than the digital function. however, if more than two analog functions are enabled and the analog signal input comes from the same external pin, the analog input will be internally connected to all of these active analog functional modules. pin-remapping register the limited number of supplied pins in a package can impose restrictions on the amount of functions a certain device can contain. however by allowing the same pins to share several different functions and providing a means of function selection, a wide range of different functions can be incorporated into even relatively small package sizes. the device includes prm register which can select the functions of certain pins.
rev. 1.30 ?? de?e??e? 1?? ?01? rev. 1.30 ?3 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu prm register bit 7 6 5 4 3 2 1 0 na?e out1hprm out1lprm out0hprm out0lprm int?prm int1prm int0prm r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 unimplemented, read as 0 bit 6 out1hprm : out1h pin remap control 0: out1h on pb2 1: out1h on pa4 bit 5 out1lprm : out1l pin remap control 0: out1l on pb1 1: out1l on pb0 bit 4 out0hprm : out0h pin remap control 0: out0h on pb3 1: out0h on pb2 bit 3 out0lprm : out0l pin remap control 0: out0l on pb4 1: out0l on pb1 bit 2 int2prm : int2 pin remap control 0: int2 on pa7 1: int2 on pa4 bit 1 int1prm : int1 pin remap control 0: int1 on pa6 1: int1 on pa3 bit 0 int0prm : int0 pin remap control 0: int0 on pa5 1: int0 on pa2 for the ht45fh4n device care must be taken when the pin-remapping function is used as the pb1~pb4 i/o lines are not connected to the external pins.
rev. 1.30 ?? de?e??e? 1?? ?01? rev. 1.30 ?5 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu i/o pin structures the accompanying diagrams illustrate the internal structures of some generic i/o pin types. as the exact logical construction of the i/o pin will differ from these drawings, they are supplied as a guide only to assist with the functional understanding of the i/o pins. the wide range of pin-shared structures does not permit all types to be shown.                     
                                           
                       ?? ?     ??      ?   ?  ?         generic input/output structure                        
                         
                          ?    ?   
 ?  ?          ?   ? -  ?  ? -  ?  ??        ? a/d input/output structure
rev. 1.30 ?? de?e??e? 1?? ?01? rev. 1.30 ?5 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu programming considerations within the user program, one of the frst things to consider is port initialisation. after a reset, all of the i/o data and port control registers will be set high. this means that all i/o pins will default to an input state, the level of which depends on the other connected circuitry and whether pull-high selections have been chosen. if the port control registers, pac~pdc, are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data registers, pa~pd, are frst programmed. selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control register using the set [m].i and clr [m].i instructions. note that when using these bit control instructions, a read-modify-write operation takes place. the microcontroller must frst read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports.                         
       read/wite timing port a has the additional capability of providing wake-up functions. when the device is in the sleep or idle mode, various methods are available to wake the device up. one of these is a high to low transition of any of the port a pins. single or multiple pins on port a can be setup to have this function. it must be noted that for the ht45fh4n, which contains a level shifter, there are three internal pins, pb1, pb2 and pd1 which are not bonded out to external pins. because after power on or during programming, these pins could be setup as logic inputs, it is recommended that these three pins are connected to internal pull high resistors to prevent them from foating and thus consuming power.
rev. 1.30 ?? de?e??e? 1?? ?01? rev. 1.30 ?7 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu timer modules C tm one of the most fundamental functions in any microcontroller device is the ability to control and measure time. to implement time related functions the device includes several timer modules, abbreviated to the name tm. the tms are multi-purpose timing units and serve to provide operations such as timer/counter, input capture, compare match output and single pulse output as well as being the functional unit for the generation of pwm signals. each of the tms has two individual interrupts. the addition of input and output pins for each tm ensures that users are provided with timing units with a wide and fexible range of features. the common features of the different tm types are described here with more detailed information provided in the individual standard and periodic tm section. introduction the device contains a 16-bit standard tm and three 10-bit periodic tms, each tm having a reference name of tm0, tm1, tm2 and tm3. although similar in nature, the different tm types vary in their feature complexity. the common features to the standard and periodic tms will be described in this section and the detailed operation will be described in corresponding sections. the main features and differences between the two types of tms are summarised in the accompanying table. function stm ptm ti ?e?/counte? i/p captu ?e co?pa?e mat?h output pwm channels 1 1 single pulse output 1 1 pwm align ?ent edge edge pwm adjust ?ent pe?iod & duty duty o? pe?iod duty o? pe?iod tm function summary device tm0 tm1 tm2 tm3 ht?5f?n / ht?5fh?n 1?-?it stm 10-?it ptm 10-?it ptm 10-?it ptm tm name/type reference tm operation the two different types of tms offer a diverse range of functions, from simple timing operations to pwm signal generation. the key to understanding how the tm operates is to see it in terms of a free running counter whose value is then compared with the value of pre-programmed internal comparators. when the free running counter has the same value as the pre-programmed comparator, known as a compare match situation, a tm interrupt signal will be generated which can clear the counter and perhaps also change the condition of the tm output pin. the internal tm counter is driven by a user selectable clock source, which can be an internal clock or an external pin. tm clock source the clock source which drives the main counter in each tm can originate from various sources. the selection of the required clock source is implemented using the tnck2~tnck0 bits in the tm control registers. the clock source can be a ratio of either the system clock f sys or the internal high clock f h , the f tbc clock source or the external tckn pin. the tckn pin clock source is used to allow an external signal to drive the tm as an external clock source or for event counting.
rev. 1.30 ?? de?e??e? 1?? ?01? rev. 1.30 ?7 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu tm interrupts the two different types of tms have two internal interrupts, the internal comparator a or comparator p, which generate a tm interrupt when a compare match condition occurs. when a tm interrupt is generated, it can be used to clear the counter and also to change the state of the tm output pin. tm external pins each of the tms, irrespective of what type, has one tm input pin, with the label tckn. the tm input pin, is essentially a clock source for the tm and is selected using the tnck2~tnck0 bits in the tmnc0 register. this external tm input pin allows an external clock source to drive the internal tm. this external tm input pin is shared with other functions but will be connected to the internal tm if selected using the tnck2~tnck0 bits. the tm input pin can be chosen to have either a rising or falling active edge. the tms each have two output pins. when the tm is in the compare match output mode, these pins can be controlled by the tm to switch to a high or low level or to toggle when a compare match situation occurs. the external tpn output pin is also the pin where the tm generates the pwm output waveform. as the tm output pins are pin-shared with other function, the tm output function must frst be setup using registers. a single bit in one of the registers determines if its associated pin is to be used as an external tm output pin or if it is to have another function. the number of output pins for each tm type is different, the details are provided in the accompanying table. tm output pin names have an _n suffx. pin names that include a _0 or _1 suffx indicate that they are from a tm with multiple output pins. this allows the tm to generate a complimentary output pair, selected using the i/o register data bits. device tm0 tm1 tm2 tm3 ht?5f?n / ht?5fh?n tp0_0? tp0_1 tp1_0? tp1_1 tp?_0? tp?_1 tp3_0? tp3_1 tm output pins tm input/output pin control register selecting to have a tm input/output or whether to retain its other shared function is implemented using one register, with a single bit in each register corresponding to a tm input/output pin. setting the bit high will setup the corresponding pin as a tm input/output, if reset to zero the pin will retain its original other function.
rev. 1.30 ?8 de?e??e? 1?? ?01? rev. 1.30 ?9 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu                       
             
                        
        tm0 function pin control block diagram note: 1. the i/o register data bits shown are used for tm output inversion control. 2. in the capture input mode, the tm pin control register must never enable more than one tm input.
rev. 1.30 ?8 de?e??e? 1?? ?01? rev. 1.30 ?9 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu                       
             
                        
              tm1 function pin control block diagram note: 1. the i/o register data bits shown are used for tm output inversion control. 2. in the capture input mode, the tm pin control register must never enable more than one tm input.
rev. 1.30 70 de?e??e? 1?? ?01? rev. 1.30 71 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu                       
            
                      
           tm2 function pin control block diagram note: 1. the i/o register data bits shown are used for tm output inversion control. 2. in the capture input mode, the tm pin control register must never enable more than one tm input.
rev. 1.30 70 de?e??e? 1?? ?01? rev. 1.30 71 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu                       
 
          
 
  
                   
 
  
    
  
 tm3 function pin control block diagram note: 1. the i/o register data bits shown are used for tm output inversion control. 2. in the capture input mode, the tm pin control register must never enable more than one tm input.
rev. 1.30 7? de?e??e? 1?? ?01? rev. 1.30 73 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu tmpc0 register bit 7 6 5 4 3 2 1 0 na?e out0ln out0hn out0cp1 out0cp0 t1cp1 t1cp0 t0cp1 t0cp0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 0 0 0 0 0 0 bit 7 out0ln : out0l signal inverting control 0: non-inverted 1: inverted this bit is used to control whether the out0l signal is inverted or not before output. bit 6 out0hn : out0h signal inverting control 0: non-inverted 1: inverted this bit is used to control whether the out0h signal is inverted or not before output. bit 5 ~ 4 out0cp[1:0]: out0h and out0l pin control 00: normal i/o function, i.e., pb4(or pb1) and pb3(or pb2) 01: pb4(or pb1) and out0h 10: out0l and pb3(or pb2) 11: out0l and out0h if these bits are set to 11, the dead time circuitry will be automatically enabled. if these bits are set to a value except 11, then the dead time circuitry will be automatically disabled note: for the ht45fh4n device care must be taken when the out0l and out0h pin functions are used as the pb1 and pb2 lines are not connected to the external pins and the pb3 and pb4 lines are internally connected to the level shift input a and c respectively. bit 3 t1cp1 : tp1_1 pin control 0: tp1_1 pin is disabled 1: tp1_1 pin is enabled bit 2 t1cp0 : tp1_0 pin control 0: tp1_0 pin is disabled 1: tp1_0 pin is enabled bit 1 t0cp1 : tp0_1 pin control 0: tp0_1 pin is disabled 1: tp0_1 pin is enabled bit 0 t0cp0 : tp0_0 pin control 0: tp0_0 pin is disabled 1: tp0_0 pin is enabled
rev. 1.30 7? de?e??e? 1?? ?01? rev. 1.30 73 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu tmpc1 register bit 7 6 5 4 3 2 1 0 na?e out1ln out1hn out1cp1 out1cp0 t3cp1 t3cp0 t?cp1 t?cp0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 0 0 0 0 0 0 bit 7 out1ln : out1l signal inverting control 0: non-inverted 1: inverted this bit is used to control whether the out1l signal is inverted or not before output. bit 6 out1hn : out1h signal inverting control 0: non-inverted 1: inverted this bit is used to control whether the out1h signal is inverted or not before output. bit 5 ~ 4 out1cp[1:0] : out1h and out1l pin control 00: normal i/o function, i.e., pb1(or pb0) and pb2(or pa4) 01: pb1(or pb0) and out1h 10: out1l and pb2(or pa4) 11: out1l and out1h if these bits are set to 11, the dead time circuitry will be automatically enabled. if these bits are set to a value except 11, then the dead time circuitry will be automatically disabled. note: for the ht45fh4n device care must be taken when the out1l and out1h pin functions are used as the pb1 and pb2 lines are not connected to the external pins and the pb3 and pb4 lines are internally connected to the level shift input a and c respectively. bit 3 t3cp1 : tp3_1 pin control 0: tp3_1 pin is disabled 1: tp3_1 pin is enabled bit 2 t3cp0 : tp3_0 pin control 0: tp3_0 pin is disabled 1: tp3_0 pin is enabled bit 1 t2cp1 : tp2_1 pin control 0: tp2_1 pin is disabled 1: tp2_1 pin is enabled bit 0 t2cp0 : tp2_0 pin control 0: tp2_0 pin is disabled 1: tp2_0 pin is enabled
rev. 1.30 7? de?e??e? 1?? ?01? rev. 1.30 75 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu programming considerations the tm counter registers, the capture/compare ccra and the ccrp registers, being either 16- bit or 10-bit, all have a low and high byte structure. the high bytes can be directly accessed, but as the low bytes can only be accessed via an internal 8-bit buffer, reading or writing to these register pairs must be carried out in a specifc way. the important point to note is that data transfer to and from the 8-bit buffer and its related low byte only takes place when a write or read operation to its corresponding high byte is executed. as the ccra and ccrp registers are implemented in the way shown in the following diagram and accessing these register pairs is carried out in a specifc way described above, it is recommended to use the mov instruction to access the ccra or ccrp low byte registers, named tmxal or tmxrpl, using the following access procedures. accessing the ccra or ccrp low byte register without following these access procedures will result in unpredictable values. data bus 8 - ?it buffe? tmxdh tmxdl tmx rp h tmx rp l tmxah tmxal tm counte? registe? ( read only ) tm ccra registe? ( read / w?ite ) tm ccr p registe? ( read / w?ite ) the following steps show the read and write procedures: ? writing data to ccra or ccrp ? step 1. write data to low byte tmxal or tmxrpl C note that here data is only written to the 8-bit buffer. ? step 2. write data to high byte tmxah or tmxrph C here data is written directly to the high byte registers and simultaneously data is latched from the 8-bit buffer to the low byte registers. ? reading data from the counter registers and ccra or ccrp ? step 1. read data from the high byte tmxdh, tmxah or tmxrph C here data is read directly from the high byte registers and simultaneously data is latched from the low byte register into the 8-bit buffer. ? step 2. read data from the low byte tmxdl, tmxal or tmxrpl C this step reads data from the 8-bit buffer.
rev. 1.30 7? de?e??e? 1?? ?01? rev. 1.30 75 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu standard type tm C stm the standard type tm contains fve operating modes, which are compare match output, timer/ event counter, capture input, single pulse output and pwm output modes. the standard tm can also be controlled with an external input pin and can drive two external output pins. these two external output pins can be the same signal or the inverse signal. name tm no. tm input pin tm output pin 1?-?it stm 0 tck0 tp0_0? tp0_1                               
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       ?  ?  ?            ? ??? ?? ? ??? ? ? ?  ? ? ? ? ? ?  ? ?   standard type tm block diagram (n=0) standard tm operation at its core is a 16-bit count-up counter which is driven by a user selectable internal or external clock source. there are also two internal comparators with the names, comparator a and comparator p. these comparators will compare the value in the counter with ccrp and ccra registers. the ccrp is 8-bits wide whose value is compared with the highest 8 bits in the counter while the ccra is the 16 bits and therefore compares with all counter bits. the only way of changing the value of the 16-bit counter using the application program, is to clear the counter by changing the t0on bit from low to high. the counter will also be cleared automatically by a counter overfow or a compare match with one of its associated comparators. when these conditions occur, a tm interrupt signal will also usually be generated. the standard type tm can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control an output pin. all operating setup conditions are selected using relevant internal registers.
rev. 1.30 7? de?e??e? 1?? ?01? rev. 1.30 77 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu standard type tm register description overall operation of the standard tm is controlled using seven registers. a read only register pair exists to store the internal counter 16-bit value, while a read/write register pair exists to store the internal 16-bit ccra value. the remaining two registers are control registers which setup the different operating and control modes as well as the eight ccrp bits. name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tm0c0 t0pau t0ck? t0ck1 t0ck0 t0on tm0c1 t0m1 t0m0 t0io1 t0io0 t0oc t0pol t0dpx t0cclr tm0dl d7 d? d5 d? d3 d? d1 d0 tm0dh d15 d1? d13 d1? d11 d10 d9 d8 tm0al d7 d? d5 d? d3 d? d1 d0 tm0ah d15 d1? d13 d1? d11 d10 d9 d8 tm0rp d7 d? d5 d? d3 d? d1 d0 16-bit standard tm register list tm0c0 register bit 7 6 5 4 3 2 1 0 na?e t0pau t0ck? t0ck1 t0ck0 t0on r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 bit 7 t0pau : tm0 counter pause control 0: run 1: pause the counter can be paused by setting this bit high. clearing the bit to zero restores normal counter operation. when in a pause condition the tm will remain powered up and continue to consume power. the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. bit 6 ~ 4 t0ck2 ~ t0ck0 : select tm0 counter clock 000: f /4 001: f 010: f h /16 011: f h /64 100: f tbc 101: f tbc 110: tck0 rising edge clock 111: tck0 falling edge clock these three bits are used to select the clock source for the tm. the external pin clock source can be chosen to be active on the rising or falling edge. the clock source f is the system clock, while f h and f tbc are other internal clocks, the details of which can be found in the oscillator section.
rev. 1.30 7? de?e??e? 1?? ?01? rev. 1.30 77 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu bit 3 t0on : tm0 counter on/off control 0: off 1: on this bit controls the overall on/off function of the tm. setting the bit high enables the counter to run, clearing the bit disables the tm. clearing this bit to zero will stop the counter from counting and turn off the tm which will reduce its power consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. if the tm is in the compare match output mode then the tm output pin will be reset to its initial condition, as specifed by the t0oc bit, when the t0on bit changes from low to high. bit 2 ~ 0 unimplemented, read as 0 tm0c1 register bit 7 6 5 4 3 2 1 0 na?e t0m1 t0m0 t0io1 t0io0 t0oc t0pol t0dpx t0cclr r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 ~ 6 t0m1~t0m0 : select tm0 operating mode 00: compare match output mode 01: capture input mode 10: pwm mode or single pulse output mode 11: timer/counter mode these bits setup the required operating mode for the tm. to ensure reliable operation the tm should be switched off before any changes are made to the bits. in the timer/ counter mode, the tm output pin control must be disabled. bit 5 ~ 4 t0io1~t0io0 : select tm0 output function compare match output mode 00: no change 01: output low 10: output high 11: toggle output pwm mode/single pulse output mode 00: force inactive state 01: force active state 10: pwm output 11: single pulse output capture input mode 00: input capture at rising edge of tm capture input pin 01: input capture at falling edge of tm capture input pin 10: input capture at falling/rising edge of tm capture input pin 11: input capture disabled timer/counter mode: unused these two bits are used to determine how the tm output pin changes state when a certain condition is reached. the function that these bits select depends upon in which mode the tm is running.
rev. 1.30 78 de?e??e? 1?? ?01? rev. 1.30 79 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu in the compare match output mode, the t0io1~t0io0 bits determine how the tm output pin changes state when a compare match occurs from the comparator a. the tm output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator a. when the t0io1~t0io0 bits are both zero, then no change will take place on the output. the initial value of the tm output pin should be setup using the t0oc bit. note that the output level requested by the t0io1~t0io0 bits must be different from the initial value setup using the t0oc bit otherwise no change will occur on the tm output pin when a compare match occurs. after the tm output pin changes state it can be reset to its initial level by changing the level of the t0on bit from low to high. in the pwm mode, the t0io1 and t0io0 bits determine how the tm output pin changes state when a certain compare match condition occurs. the pwm output function is modifed by changing these two bits. it is necessary to change the values of the t0io1 and t0io0 bits only after the tm has been switched off. unpredictable pwm outputs will occur if the t0io1 and t0io0 bits are changed when the tm is running. bit 3 t0oc : tm0 output control bit compare match output mode 0: initial low 1: initial high pwm mode/ single pulse output mode 0: active low 1: active high this is the output control bit for the tm output pin. its operation depends upon whether tm is being used in the compare match output mode or in the pwm mode/ single pulse output mode. it has no effect if the tm is in the timer/counter mode. in the compare match output mode it determines the logic level of the tm output pin before a compare match occurs. in the pwm mode it determines if the pwm signal is active high or active low. bit 2 t0pol : tm0 output polarity control 0: non-invert 1: invert this bit controls the polarity of the tm output pin. when the bit is set high the tm output pin will be inverted and not inverted when the bit is zero. it has no effect if the tm is in the timer/counter mode. bit 1 t0dpx : tm0 pwm period/duty control 0: ccrp - period; ccra - duty 1: ccrp - duty; ccra - period this bit, determines which of the ccra and ccrp registers are used for period and duty control of the pwm waveform. bit 0 t0cclr : select tm0 counter clear condition 0: tm comparatror p match 1: tm comparatror a match this bit is used to select the method which clears the counter. remember that the standard tm contains two comparators, comparator a and comparator p, either of which can be selected to clear the internal counter. with the t0cclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low, the counter will be cleared when a compare match occurs from the comparator p or with a counter overfow. a counter overfow clearing method can only be implemented if the ccrp bits are all cleared to zero. the t0cclr bit is not used in the pwm, single pulse or input capture mode.
rev. 1.30 78 de?e??e? 1?? ?01? rev. 1.30 79 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu tm0dl register bit 7 6 5 4 3 2 1 0 na?e d7 d? d5 d? d3 d? d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7 ~ 0 tm0dl : tm0 counter low byte register bit 7 ~ bit 0 tm 16-bit counter bit 7 ~ bit 0 tm0dh register bit 7 6 5 4 3 2 1 0 na?e d15 d1? d13 d1? d11 d10 d9 d8 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7 ~ 0 tm0dh : tm0 counter high byte register bit 7 ~ bit 0 tm 16-bit counter bit 15 ~ bit 8 tm0al register bit 7 6 5 4 3 2 1 0 na?e d7 d? d5 d? d3 d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 ~ 0 tm0al : tm0 ccra low byte register bit 7 ~ bit 0 tm 16-bit ccra bit 7 ~ bit 0 tm0ah register bit 7 6 5 4 3 2 1 0 na?e d15 d1? d13 d1? d11 d10 d9 d8 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 ~ 0 tm0ah : tm0 ccra high byte register bit 7 ~ bit 0 tm 16-bit ccra bit 15 ~ bit 8
rev. 1.30 80 de?e??e? 1?? ?01? rev. 1.30 81 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu tm0rp register bit 7 6 5 4 3 2 1 0 na?e d7 d? d5 d? d3 d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 ~ 0 tm0rp : tm0 ccrp high byte register bit 7 ~ bit 0 tm0 ccrp 8-bit register, compared with the tm0 counter bit 15 ~ bit 8. comparator p match period 0: 65536 tm0 clocks 1~255: 256 (1~255) tm0 clocks these eight bits are used to setup the value on the internal ccrp 8-bit register, which are then compared with the internal counters highest eight bits. the result of this comparison can be selected to clear the internal counter if the t0cclr bit is set to zero. setting the t0cclr bit to zero ensures that a compare match with the ccrp values will reset the internal counter. as the ccrp bits are only compared with the highest eight counter bits, the compare values exist in 256 clock cycle multiples. clearing all eight bits to zero is in effect allowing the counter to overflow at its maximum value. standard type tm operating modes the standard type tm can operate in one of fve operating modes, compare match output mode, pwm output mode, single pulse output mode, capture input mode or timer/counter mode. the operating mode is selected using the t0m1 and t0m0 bits in the tm0c1 register. compare output mode to select this mode, bits t0m1 and t0m0 in the tm0c1 register, should be set to 00 respectively. in this mode once the counter is enabled and running it can be cleared by three methods. these are a counter overfow, a compare match from comparator a and a compare match from comparator p. when the t0cclr bit is low, there are two ways in which the counter can be cleared. one is when a compare match from comparator p, the other is when the ccrp bits are all zero which allows the counter to overfow. here both t0af and t0pf interrupt request fags for comparator a and comparator p respectively, will both be generated. if the t0cclr bit in the tm0c1 register is high then the counter will be cleared when a compare match occurs from comparator a. however, here only the t0af interrupt request flag will be generated even if the value of the ccrp bits is less than that of the ccra registers. therefore when t0cclr is high no t0pf interrupt request fag will be generated. in the compare match output mode, the ccra can not be set to 0. as the name of the mode suggests, after a comparison is made, the tm output pin, will change state. the tm output pin condition however only changes state when a t0af interrupt request fag is generated after a compare match occurs from comparator a. the t0pf interrupt request flag, generated from a compare match occurs from comparator p, will have no effect on the tm output pin. the way in which the tm output pin changes state are determined by the condition of the t0io1 and t0io0 bits in the tm0c1 register. the tm output pin can be selected using the t0io1 and t0io0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from comparator a. the initial condition of the tm output pin, which is setup after the t0on bit changes from low to high, is setup using the t0oc bit. note that if the t0io1 and t0io0 bits are zero then no pin change will take place.
rev. 1.30 80 de?e??e? 1?? ?01? rev. 1.30 81 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu ccra ccrp 0xffff counte ? ove ? flow ccra int. flag tnaf ccrp int. flag tnpf ccrp > 0 counte ? ? lea ? ed ? y ccrp value tm o/p pin tnon pause counte ? reset output pin set to initial level low if tnoc = 0 output tog g le with tnaf flag he ? e tnio1 ? tnio0 = 11 tog g le output sele ? t now tnio1 ? tnio0 = 10 a ? tive hig h output sele ? t output not affe ? ted ?y tnaf flag . re ? ains hig h until ? eset ? y tnon ? it tncclr = 0; tnm[1:0] = 00 tn pau resu ? e stop ti ?e ccrp > 0 ccrp = 0 tn pol output pin reset to initial value output inve ? ts when tnpol is hig h output ? ont ? olled ? y othe? pin - sha ? ed fun ? tion counte ? value compare match output mode tncclr=0 note: 1. with tncclr = 0 a comparator p match will clear the counter 2. the tm output pin controlled only by the tnaf fag 3. the output pin reset to initial state by a tnon bit rising edge 4. n = 0
rev. 1.30 8? de?e??e? 1?? ?01? rev. 1.30 83 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu ccrp ccra 0xffff ccra = 0 counte ? ove ? flows ccrp int. flag tnpf ccra int. flag tnaf ccra > 0 counte ? ? lea ? ed ? y ccra value tm o/p pin tnon pause counte ? reset output pin reset to initial value output pin set to initial level low if tnoc = 0 output tog g le with tnaf flag he ? e tnio1 ? tnio0 = 11 tog g le output sele ? t now tnio1 ? tnio0 = 10 a ? tive hig h output sele ? t tn pau resu ? e stop ti ?e tnpf not g ene ? ated no tnaf flag g ene ? ated on ccra ove ? flow output does not ? hang e ccra = 0 output inve ? ts when tnpol is hig h tn pol tncclr = 1; tnm[1:0] = 00 output ? ont ? olled ?y othe ? pin - sha ? ed fun ? tion output not affe ? ted ?y tnaf flag ? e? ains hig h until ? eset ? y tnon ? it counte ? value compare match output mode tncclr=1 note: 1. with tncclr = 1 a comparator a match will clear the counter 2. the tm output pin controlled only by the tnaf fag 3. the output pin reset to initial state by a tnon rising edge 4. the tnpf fag is not generated when tncclr = 1 5. n = 0
rev. 1.30 8? de?e??e? 1?? ?01? rev. 1.30 83 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu timer/counter mode to select this mode, bits t0m1 and t0m0 in the tm0c1 register should be set to 11 respectively. the timer/counter mode operates in an identical way to the compare match output mode generating the same interrupt fags. the exception is that in the timer/counter mode the tm output pin is not used. therefore the above description and timing diagrams for the compare match output mode can be used to understand its function. as the tm output pin is not used in this mode, the pin can be used as a normal i/o pin or other pin-shared function. pwm output mode to select this mode, bits t0m1 and t0m0 in the tm0c1 register should be set to 10 respectively and also the t0io1 and t0io0 bits should be set to 10 respectively. the pwm function within the tm is useful for applications which require functions such as motor control, heating control, illumination control etc. by providing a signal of fxed frequency but of varying duty cycle on the tm output pin, a square wave ac waveform can be generated with varying equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform is extremely flexible. in the pwm mode, the t0cclr bit has no effect as the pwm period. both of the ccra and ccrp registers are used to generate the pwm waveform, one register is used to clear the internal counter and thus control the pwm waveform frequency, while the other one is used to control the duty cycle. which register is used to control either frequency or duty cycle is determined using the t0dpx bit in the tm0c1 register. the pwm waveform frequency and duty cycle can therefore be controlled by the values in the ccra and ccrp registers. an interrupt flag, one for each of the ccra and ccrp, will be generated when a compare match occurs from either comparator a or comparator p. the t0oc bit in the tm0c1 register is used to select the required polarity of the pwm waveform while the two t0io1 and t0io0 bits are used to enable the pwm output or to force the tm output pin to a fxed high or low level. the t0pol bit is used to reverse the polarity of the pwm output waveform. 16-bit stm, pwm mode, edge-aligned mode, t0dpx=0 ccrp 1~255 0 pe?iod ccrp?5? ?553? duty ccra if f sys = 30 mhz, tm clock source is f sys /4, ccrp = 2 and ccra =128, the stm pwm output frequency = (f sys /4) / 512 = f sys /2048 = 14.65 khz, duty = 128/ 512 = 25%. if the duty value defned by the ccra register is equal to or greater than the period value, then the pwm output duty is 100%. 16-bit stm, pwm mode, edge-aligned mode, t0dpx=1 ccrp 1~255 0 pe?iod ccra duty ccrp?5? ?553? the pwm output period is determined by the ccra register value together with the tm clock while the pwm duty cycle is defned by the (ccrp256) except when the ccrp value is equal to 0.
rev. 1.30 8? de?e??e? 1?? ?01? rev. 1.30 85 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu counte? value ccrp ccra tnon tnpau tnpol ccrp int . flag tnpf ccra int . flag tnaf tm o / p pin ( tnoc = 1 ) ti?e counte? ?lea?ed ?y ccrp pause resu?e counte? stop if tnon ?it low counte? reset when tnon ?etu?ns high tndpx = 0 ; tnm [ 1 : 0 ] = 10 pwm duty cy?le set ?y ccra pwm ?esu?es ope?ation output ?ont?olled ?y othe? pin - sha?ed fun?tion output inve?ts when tnpol = 1 pwm pe?iod set ?y ccrp tm o / p pin ( tnoc = 0 ) pwm mode tndpx=0 note: 1. here tndpx = 0 - counter cleared by ccrp 2. a counter clear sets pwm period 3. the internal pwm function continues running even when tnio[1:0] = 00 or 01 4. the tncclr bit has no infuence on pwm operation 5. n = 0
rev. 1.30 8? de?e??e? 1?? ?01? rev. 1.30 85 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu counte? value ccrp ccra tnon tnpau tnpol ccrp int . flag tnpf ccra int . flag tnaf tm o / p pin ( tnoc = 1 ) ti?e counte? ?lea?ed ?y ccra pause resu?e counte? stop if tnon ?it low counte? reset when tnon ?etu?ns high tndpx = 1 ; tnm [ 1 : 0 ] = 10 pwm duty cy?le set ?y ccrp pwm ?esu?es ope?ation output ?ont?olled ?y othe? pin - sha?ed fun?tion output inve?ts when tnpol = 1 pwm pe?iod set ?y ccra tm o / p pin ( tnoc = 0 ) pwm mode tndpx=1 note: 1. here tndpx = 1 - counter cleared by ccra 2. a counter clear sets pwm period 3. the internal pwm function continues even when tnio[1:0] = 00 or 01 4. the tncclr bit has no infuence on pwm operation 5. n = 0
rev. 1.30 8? de?e??e? 1?? ?01? rev. 1.30 87 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu single pulse output mode to select this mode, bits t0m1 and t0m0 in the tm0c1 register should be set to 10 respectively and also the t0io1 and t0io0 bits should be set to 11 respectively. the single pulse output mode, as the name suggests, will generate a single shot pulse on the tm output pin. the trigger for the pulse output leading edge is a low to high transition of the t0on bit, which can be implemented using the application program. however in the single pulse mode, the t0on bit can also be made to automatically change from low to high using the external tck0 pin, which will in turn initiate the single pulse output. when the t0on bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. the t0on bit should remain high when the pulse is in its active state. the generated pulse trailing edge will be generated when the t0on bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from comparator a.             
                         
             
?  ? ?     ?   ? ? ?   ?      ? ? ?   single pulse generation (n=0)
rev. 1.30 8? de?e??e? 1?? ?01? rev. 1.30 87 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu counte? value ccrp ccra tnon tnpau tnpol ccrp int . flag tnpf ccra int . flag tnaf tm o / p pin ( tnoc = 1 ) ti?e counte? stopped ?y ccra pause resu?e counte? stops ?y softwa?e counte? reset when tnon ?etu?ns high tnm [ 1 : 0 ] = 10 ; tnio [ 1 : 0 ] = 11 pulse width set ?y ccra output inve?ts when tnpol = 1 no ccrp inte??upts gene?ated tm o / p pin ( tnoc = 0 ) tckn pin softwa?e t?igge? clea?ed ?y ccra ?at?h tckn pin t?igge? auto . set ?y tckn pin softwa?e t?igge? softwa?e clea? softwa?e t?igge? softwa?e t?igge? single pulse output mode note: 1. counter stopped by ccra match 2. ccrp is not used 3. the pulse is triggered by the tckn pin or setting the tnon bit high 4. a tckn pin active edge will automatically set the tnon bit high 5. in the single pulse mode, tnio [1:0] must be set to 11 and can not be changed. 6. n = 0 however a compare match from comparator a will also automatically clear the t0on bit and thus generate the single pulse output trailing edge. in this way the ccra value can be used to control the pulse width. a compare match from comparator a will also generate a tm interrupt. the counter can only be reset back to zero when the t0on bit changes from low to high when the counter restarts. in the single pulse mode ccrp is not used. the t0cclr and t0dpx bits are not used in this mode.
rev. 1.30 88 de?e??e? 1?? ?01? rev. 1.30 89 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu capture input mode to select this mode bits t0m1 and t0m0 in the tm0c1 register should be set to 01 respectively. this mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. the external signal is supplied on the tp0_0 or tp0_1 pin, whose active edge can be either a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the t0io1 and t0io0 bits in the tm0c1 register. the counter is started when the t0on bit changes from low to high which is initiated using the application program. when the required edge transition appears on the tp0_0 or tp0_1 pin the present value in the counter will be latched into the ccra registers and a tm interrupt generated. irrespective of what events occur on the tp0_0 or tp0_1 pin the counter will continue to free run until the tnon bit changes from high to low. when a ccrp compare match occurs the counter will reset back to zero; in this way the ccrp value can be used to control the maximum counter value. when a ccrp compare match occurs from comparator p, a tm interrupt will also be generated. counting the number of overflow interrupt signals from the ccrp can be a useful method in measuring long pulse widths. the tnio1 and tnio0 bits can select the active trigger edge on the tp0_0 or tp0_1 pin to be a rising edge, falling edge or both edge types. if the tnio1 and tnio0 bits are both set high, then no capture operation will take place irrespective of what happens on the tp0_0 or tp0_1 pin, however it must be noted that the counter will continue to run. as the tp0_0 or tp0_1 pin is pin shared with other functions, care must be taken if the tm is in the input capture mode. this is because if the pin is setup as an output, then any transitions on this pin may cause an input capture operation to be executed. the t0cclr and t0dpx bits are not used in this mode.
rev. 1.30 88 de?e??e? 1?? ?01? rev. 1.30 89 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu counte? value yy ccrp tnon tnpau ccrp int . flag tnpf ccra int . flag tnaf ccra value ti?e counte? ?lea?ed ?y ccrp pause resu?e counte? reset tnm [ 1 : 0 ] = 01 tm ?aptu?e pin tpn _ x xx counte? stop tnio [ 1 : 0 ] value xx yy xx yy a?tive edge a?tive edge a?tive edge 00 C rising edge 01 C falling edge 10 C both edges 11 C disa?le captu?e capture input mode note: 1. tnm[1:0] = 01 and active edge set by the tnio[1:0] bits 2. a tm capture input pin active edge transfers the counter value to ccra 3. the tncclr bit is not used 4. no output function - tnoc and tnpol bits are not used 5. ccrp determines the counter value and the counter has a maximum count value when ccrp is equal to zero. 6. n = 0
rev. 1.30 90 de?e??e? 1?? ?01? rev. 1.30 91 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu periodic type tm C ptm the periodic type tm contains fve operating modes, which are compare match output, timer/ event counter, capture input, single pulse output and pwm output modes. the periodic tm can also be controlled with an external input pin and can drive one external output pin. periodic tm operation at its core is a 10-bit count-up counter which is driven by a user selectable internal or external clock source. there are two internal comparators with the names, comparator a and comparator p. these comparators will compare the value in the counter with the ccra and ccrp registers. the only way of changing the value of the 10-bit counter using the application program, is to clear the counter by changing the tnon bit from low to high. the counter will also be cleared automatically by a counter overfow or a compare match with one of its associated comparators. when these conditions occur, a tm interrupt signal will also usually be generated. the periodic type tm can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control the output pin. all operating setup conditions are selected using relevant internal registers.                             
                                             ? ?    ? ?       ?  ?
      ? ?? -     ?
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  ?    ?
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     ?    
        ?             ? ??? ?? ? ??? ? ? ? ? ? ? ?? ? ? ?  ? ?      ?  ?  ?   ?  periodic type tm block diagram (n=1~3)
rev. 1.30 90 de?e??e? 1?? ?01? rev. 1.30 91 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu periodic type tm register description overall operation of the periodic tm is controlled using a series of registers. a read only register pair exists to store the internal counter 10-bit value, while two read/write register pairs exist to store the internal 10-bit ccra and ccrp value. the remaining two registers are control registers which setup the different operating and control modes. name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tmnc0 tnpau tnck? tnck1 tnck0 tnon tmnc1 tnm1 tnm0 tnio1 tnio0 tnoc tnpol tncapts tncclr tmndl d7 d? d5 d? d3 d? d1 d0 tmndh d9 d8 tmnal d7 d? d5 d? d3 d? d1 d0 tmnah d9 d8 tmnrpl d7 d? d5 d? d3 d? d1 d0 tmnrph d9 d8 10-bit periodic tm register list(n=1~3) tmnc0 register bit 7 6 5 4 3 2 1 0 na?e tnpau tnck? tnck1 tnck0 tnon r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 bit 7 tnpau : tmn counter pause control 0: run 1: pause the counter can be paused by setting this bit high. clearing the bit to zero restores normal counter operation. when in a pause condition the tm will remain powered up and continue to consume power. the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. bit 6 ~ 4 tnck2 ~ tnck0 : select tmn counter clock 000: f /4 001: f 010: f h /16 011: f h /64 100: f tbc 101: f h 110: tck rising edge clock 111: tck falling edge clock these three bits are used to select the clock source for the tm. the external pin clock source can be chosen to be active on the rising or falling edge. the clock source f is the system clock, while f h and f tbc are other internal clocks, the details of which can be found in the oscillator section.
rev. 1.30 9? de?e??e? 1?? ?01? rev. 1.30 93 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu bit 3 tnon : tmn counter on/off control 0: off 1: on this bit controls the overall on/off function of the tm. setting the bit high enables the counter to run, clearing the bit disables the tm. clearing this bit to zero will stop the counter from counting and turn off the tm which will reduce its power consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. if the tm is in the compare match output mode then the tm output pin will be reset to its initial condition, as specifed by the tm output control bit, when the bit changes from low to high. bit 2 ~ 0 unimplemented, read as 0 tmnc1 register bit 7 6 5 4 3 2 1 0 na?e tnm1 tnm0 tnio1 tnio0 tnoc tnpol tncapts tncclr r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 ~ 6 tnm1~tnm0 : select tmn operation mode 00: compare match output mode 01: capture input mode 10: pwm mode or single pulse output mode 11: timer/counter mode these bits setup the required operating mode for the tm. to ensure reliable operation the tm should be switched off before any changes are made to the tnm1 and tnm0 bits. in the timer/counter mode, the tm output pin control must be disabled. bit 5 ~ 4 tnio1~tnio0 : select tpn_0, tpn_1 output function compare match output mode 00: no change 01: output low 10: output high 11: toggle output pwm mode/single pulse output mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: single pulse output capture input mode 00: input capture at rising edge of tpn_0, tpn_1 01: input capture at falling edge of tpn_0, tpn_1 10: input capture at falling/rising edge of tpn_0, tpn_1 11: input capture disabled timer/counter mode unused these two bits are used to determine how the tm output pin changes state when a certain condition is reached. the function that these bits select depends upon in which mode the tm is running.
rev. 1.30 9? de?e??e? 1?? ?01? rev. 1.30 93 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu in the compare match output mode, the tnio1 and tnio0 bits determine how the tm output pin changes state when a compare match occurs from the comparator a. the tm output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator a. when these bits are both zero, then no change will take place on the output. the initial value of the tm output pin should be setup using the tnoc bit. note that the output level requested by the tnio1 and tnio0 bits must be different from the initial value setup using the tnoc bit otherwise no change will occur on the tm output pin when a compare match occurs. after the tm output pin changes state it can be reset to its initial level by changing the level of the tnon bit from low to high. in the pwm mode, the tnio1 and tnio0 bits determine how the tm output pin changes state when a certain compare match condition occurs. the pwm output function is modifed by changing these two bits. it is necessary to change the values of the tnio1 and tnio0 bits only after the tm has been switched off. unpredictable pwm outputs will occur if the tnio1 and tnio0 bits are changed when the tm is running. bit 3 tnoc : tpn_0, tpn_1 output control bit compare match output mode 0: initial low 1: initial high pwm mode/ single pulse output mode 0: active low 1: active high this is the output control bit for the tm output pin. its operation depends upon whether tm is being used in the compare match output mode or in the pwm mode/ single pulse output mode. it has no effect if the tm is in the timer/counter mode. in the compare match output mode it determines the logic level of the tm output pin before a compare match occurs. in the pwm mode it determines if the pwm signal is active high or active low. bit 2 tnpol : tpn_0, tpn_1 output polarity control 0: non-invert 1: invert this bit controls the polarity of the tpn_0, tpn_1 output pin. when the bit is set high the tm output pin will be inverted and not inverted when the bit is zero. it has no effect if the tm is in the timer/counter mode. bit 1 tncapts : tmn capture trigger source select 0: from tpn_0, tpn_1 pin 1: from tckn pin bit 0 tncclr : select tmn counter clear condition 0: tmn comparatror p match 1: tmn comparatror a match this bit is used to select the method which clears the counter. remember that the periodic tm contains two comparators, comparator a and comparator p, either of which can be selected to clear the internal counter. with the tncclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low, the counter will be cleared when a compare match occurs from the comparator p or with a counter overfow. a counter overfow clearing method can only be implemented if the ccrp bits are all cleared to zero. the tncclr bit is not used in the pwm, single pulse or input capture mode.
rev. 1.30 9? de?e??e? 1?? ?01? rev. 1.30 95 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu tmndl register bit 7 6 5 4 3 2 1 0 na?e d7 d? d5 d? d3 d? d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7 ~ 0 tmndl : tmn counter low byte register bit 7 ~ bit 0 tmn 10-bit counter bit 7 ~ bit 0 tmndh register bit 7 6 5 4 3 2 1 0 na?e d9 d8 r/w r r por 0 0 bit 7 ~ 2 unimplemented, read as 0 bit 1 ~ 0 tmndh : tmn counter high byte register bit 1 ~ bit 0 tmn 10-bit counter bit 9 ~ bit 8 tmnal register bit 7 6 5 4 3 2 1 0 na?e d7 d? d5 d? d3 d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 ~ 0 tmnal : tmn ccra low byte register bit 7 ~ bit 0 tmn 10-bit ccra bit 7 ~ bit 0 tmnah register bit 7 6 5 4 3 2 1 0 na?e d9 d8 r/w r/w r/w por 0 0 bit 7 ~ 2 unimplemented, read as 0 bit 1 ~ 0 tmnah : tmn ccra high byte register bit 1 ~ bit 0 tmn 10-bit ccra bit 9 ~ bit 8 tmnrpl register bit 7 6 5 4 3 2 1 0 na?e d7 d? d5 d? d3 d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 ~ 0 tmnrpl : tmn ccrp low byte register bit 7 ~ bit 0 tmn 10-bit ccrp bit 7 ~ bit 0
rev. 1.30 9? de?e??e? 1?? ?01? rev. 1.30 95 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu tmnrph register bit 7 6 5 4 3 2 1 0 na?e d9 d8 r/w r/w r/w por 0 0 bit 7 ~ 2 unimplemented, read as 0 bit 1 ~ 0 tmnrph : tmn ccrp high byte register bit 1 ~ bit 0 tmn 10-bit ccrp bit 9 ~ bit 8 periodic type tm operating modes the periodic type tm can operate in one of fve operating modes, compare match output mode, pwm output mode, single pulse output mode, capture input mode or timer/counter mode. the operating mode is selected using the tnm1 and tnm0 bits in the tmnc1 register. compare match output mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register, should be all cleared to 00 respectively. in this mode once the counter is enabled and running it can be cleared by three methods. these are a counter overfow, a compare match from comparator a and a compare match from comparator p. when the tncclr bit is low, there are two ways in which the counter can be cleared. one is when a compare match occurs from comparator p, the other is when the ccrp bits are all zero which allows the counter to overfow. here both the tnaf and tnpf interrupt request fags for comparator a and comparator p respectively, will both be generated. if the tncclr bit in the tmnc1 register is high then the counter will be cleared when a compare match occurs from comparator a. however, here only the tnaf interrupt request flag will be generated even if the value of the ccrp bits is less than that of the ccra registers. therefore when tncclr is high no tnpf interrupt request fag will be generated. in the compare match output mode, the ccra can not be set to 0. as the name of the mode suggests, after a comparison is made, the tm output pin, will change state. the tm output pin condition however only changes state when a tnaf interrupt request fag is generated after a compare match occurs from comparator a. the tnpf interrupt request flag, generated from a compare match from comparator p, will have no effect on the tm output pin. the way in which the tm output pin changes state are determined by the condition of the tnio1 and tnio0 bits in the tmnc1 register. the tm output pin can be selected using the tnio1 and tnio0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from comparator a. the initial condition of the tm output pin, which is setup after the tnon bit changes from low to high, is setup using the tnoc bit. note that if the tnio1, tnio0 bits are zero then no pin change will take place.
rev. 1.30 9? de?e??e? 1?? ?01? rev. 1.30 97 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu counte? value 0x3ff ccrp ccra tnon tnpau tnpol ccrp int. flag tnpf ccra int. flag tnaf tm o/p pin ti?e ccrp=0 ccrp > 0 counte? ove?flow ccrp > 0 counte? ?lea?ed ?y ccrp value pause resu?e stop counte? resta?t tncclr = 0; tnm [1:0] = 00 output pin set to initial level low if tnoc=0 output toggle with tnaf flag note tnio [1:0] = 10 a?tive high output sele?t he?e tnio [1:0] = 11 toggle output sele?t output not affe?ted ?y tnaf flag. re?ains high until ?eset ?y tnon ?it output pin reset to initial value output ?ont?olled ?y othe? pin-sha?ed fun?tion output inve?ts when tnpol is high compare match output mode C tncclr = 0 note: 1. with tncclr = 0 a comparator p match will clear the counter 2. the tm output pin is controlled only by the tnaf fag 3. the output pin is reset to initial state by a tnon bit rising edge 4. n=1~3
rev. 1.30 9? de?e??e? 1?? ?01? rev. 1.30 97 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu counte? value 0x3ff ccrp ccra tnon tnpau tnpol ccrp int. flag tnpf ccra int. flag tnaf tm o/p pin ti?e ccra=0 ccra = 0 counte? ove?flow ccra > 0 counte? ?lea?ed ?y ccra value pause resu?e stop counte? resta?t tncclr = 1; tnm [1:0] = 00 output pin set to initial level low if tnoc=0 output toggle with tnaf flag note tnio [1:0] = 10 a?tive high output sele?t he?e tnio [1:0] = 11 toggle output sele?t output not affe?ted ?y tnaf flag. re?ains high until ?eset ?y tnon ?it output pin reset to initial value output ?ont?olled ?y othe? pin-sha?ed fun?tion output inve?ts when tnpol is high tnpf not gene?ated no tnaf flag gene?ated on ccra ove?flow output does not ?hange compare match output mode C tncclr = 1 note: 1. with tncclr = 1 a comparator a match will clear the counter 2. the tm output pin is controlled only by the tnaf fag 3. the output pin is reset to initial state by a tnon rising edge 4. the tnpf fag is not generated when tncclr = 1 5. n=1~3
rev. 1.30 98 de?e??e? 1?? ?01? rev. 1.30 99 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu timer/counter mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register should all be set to 11 respectively. the timer/counter mode operates in an identical way to the compare match output mode generating the same interrupt fags. the exception is that in the timer/counter mode the tm output pin is not used. therefore the above description and timing diagrams for the compare match output mode can be used to understand its function. as the tm output pin is not used in this mode, the pin can be used as a normal i/o pin or other pin-shared function. pwm output mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register should be set to 10 respectively and also the tnio1 and tnio0 bits should be set to 10 respectively. the pwm function within the tm is useful for applications which require functions such as motor control, heating control, illumination control etc. by providing a signal of fxed frequency but of varying duty cycle on the tm output pin, a square wave ac waveform can be generated with varying equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform is extremely flexible. in the pwm mode, the tncclr bit has no effect as the pwm period. both of the ccrp and ccra registers are used to generate the pwm waveform, one register is used to clear the internal counter and thus control the pwm waveform frequency, while the other one is used to control the duty cycle. the pwm waveform frequency and duty cycle can therefore be controlled by the values in the ccra and ccrp registers. an interrupt fag, one for each of the ccra and ccrp, will be generated when a compare match occurs from either comparator a or comparator p. the tnoc bit in the tmnc1 register is used to select the required polarity of the pwm waveform while the two tnio1 and tnio0 bits are used to enable the pwm output or to force the tm output pin to a fxed high or low level. the tnpol bit is used to reverse the polarity of the pwm output waveform. 10-bit ptm, pwm mode ccrp 1~1023 0 pe?iod 1~10?3 10?? duty ccra if f h = 30mhz, tm clock source select f h , ccrp = 200 and ccra = 50, the ptm pwm output frequency = (f h ) / 200 = 30mhz/200 = 150 khz, duty = 50/200 = 25% if the duty value defned by the ccra register is equal to or greater than the period value, then the pwm output duty is 100%.
rev. 1.30 98 de?e??e? 1?? ?01? rev. 1.30 99 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu counte? value ccrp ccra t n on t n pau t n pol ccrp int . flag t n pf ccra int . flag t n af tm o / p pin ( t n oc = 1 ) ti?e counte? ?lea?ed ?y ccrp pause resu?e counte? stop if t n on ?it low counte? reset when t n on ?etu?ns high tndpx = 0 ; t n m [ 1 : 0 ] = 10 pwm duty cy?le set ?y ccra pwm ?esu?es ope?ation output ?ont?olled ?y othe? pin - sha?ed fun?tion output inve?ts when t n pol = 1 pwm pe?iod set ?y ccrp tm o / p pin ( t n oc = 0 ) pwm mode note: 1. here counter cleared by ccrp 2. a counter clear sets the pwm period 3. the internal pwm function continues running even when tnio[1:0] = 00 or 01 4. the tncclr bit has no infuence on pwm operation 5. n=1~3
rev. 1.30 100 de?e??e? 1?? ?01? rev. 1.30 101 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu single pulse output mode to select this mode, the required bit pairs, tnm1 and tnm0 should be set to 10 respectively and also the corresponding tnio1 and tnio0 bits should be set to 11 respectively. the single pulse output mode, as the name suggests, will generate a single shot pulse on the tm output pin. the trigger for the pulse output leading edge is a low to high transition of the tnon bit, which can be implemented using the application program. however in the single pulse mode, the tnon bit can also be made to automatically change from low to high using the external tckn pin, which will in turn initiate the single pulse output. when the tnon bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. the tnon bit should remain high when the pulse is in its active state. the generated pulse trailing edge will be generated when the tnon bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from comparator a. however a compare match from comparator a will also automatically clear the tnon bit and thus generate the single pulse output trailing edge. in this way the ccra value can be used to control the pulse width. a compare match from comparator a will also generate tm interrupts. the counter can only be reset back to zero when the tnon bit changes from low to high when the counter restarts. in the single pulse mode ccrp is not used. the tncclr bit is also not used.             
                         
             
?  ? ?     ?   ? ? ?   ?      ? ? ?   single pulse generation (n=1~3)
rev. 1.30 100 de?e??e? 1?? ?01? rev. 1.30 101 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu counte? value ccrp ccra tnon tnpau tnpol ccrp int. flag tnpf ccra int. flag tnaf tm o/p pin (tnoc=1) ti?e counte? stopped ?y ccra pause resu?e counte? stops ?y softwa?e counte? reset when tnon ?etu?ns high tnm [1:0] = 10 ; tnio [1:0] = 11 pulse width set ?y ccra output inve?ts when tnpol = 1 no ccrp inte??upts gene?ated tm o/p pin (tnoc=0) tckn pin softwa?e t?igge? clea?ed ?y ccra ?at?h tckn pin t?igge? auto. set ?y tckn pin softwa?e t?igge? softwa?e clea? softwa?e t?igge? softwa?e t?igge? single pulse output mode note: 1. counter stopped by ccra 2. ccrp is not used 3. the pulse is triggered by the tckn pin or by setting the tnon bit high 4. a tckn pin active edge will automatically set the tnon bit high 5. in the single pulse mode, tnio [1:0] must be set to 11 and can not be changed. 6. n=1~3
rev. 1.30 10? de?e??e? 1?? ?01? rev. 1.30 103 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu capture input mode to select this mode bits tnm1 and tnm0 in the tmnc1 register should be set to 01 respectively. this mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. the external signal is supplied on the tpn_0, tpn_1or tckn pin, selected by the tncapts bit in the tmnc0 register. the input pin active edge can be either a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the tnio1 and tnio0 bits in the tmnc1 register. the counter is started when the tnon bit changes from low to high which is initiated using the application program. when the required edge transition appears on the tpn_0, tpn_1 or tckn pin the present value in the counter will be latched into the ccra register and a tm interrupt generated. irrespective of what events occur on the tpn_0, tpn_1or tckn pin the counter will continue to free run until the tnon bit changes from high to low. when a ccrp compare match occurs the counter will reset back to zero; in this way the ccrp value can be used to control the maximum counter value. when a ccrp compare match occurs from comparator p, a tm interrupt will also be generated. counting the number of overfow interrupt signals from the ccrp can be a useful method in measuring long pulse widths. the tnio1 and tnio0 bits can select the active trigger edge on the tpn_0, tpn_1 or tckn pin to be a rising edge, falling edge or both edge types. if the tnio1 and tnio0 bits are both set high, then no capture operation will take place irrespective of what happens on the tpn_0, tpn_1 or tckn pin, however it must be noted that the counter will continue to run. as the tpn_0, tpn_1 or tckn pin is pin shared with other functions, care must be taken if the tmn is in the capture input mode. this is because if the pin is setup as an output, then any transitions on this pin may cause an input capture operation to be executed. the tncclr, tnoc and tnpol bits are not used in this mode.
rev. 1.30 10? de?e??e? 1?? ?01? rev. 1.30 103 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu counte? value yy ccrp tnon tnpau ccrp int. flag tnpf ccra int. flag tnaf ccra value ti?e counte? ?lea?ed ?y ccrp pause resu?e counte? reset tnm [1:0] = 01 tm ?aptu?e pin tpn_x o? tckn xx counte? stop tnio [1:0] value xx yy xx yy a?tive edge a?tive edge a?tive edge 00 C rising edge 01 C falling edge 10 C both edges 11 C disa?le captu?e capture input mode note: 1. tnm[1:0] = 01 and active edge set by the tnio[1:0] bits 2. a tm capture input pin active edge transfers counter value to ccra 3. the tncclr bit is not used 4. no output function C tnoc and tnpol bits are not used 5. ccrp determines the counter value and the counter has a maximum count value when ccrp is equal to zero 6. n=1~3
rev. 1.30 10? de?e??e? 1?? ?01? rev. 1.30 105 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu analog to digital converter the need to interface to real world analog signals is a common requirement for many electronic systems. however, to properly process these signals by a microcontroller, they must first be converted into digital signals by a/d converters. by integrating the a/d conversion electronic circuitry into the microcontroller, the need for external components is reduced signifcantly with the corresponding follow-on benefts of lower costs and reduced component space requirements. a/d overview the device contains a multi-channel analog to digital converter which can directly interface to external analog signals, such as that from sensors or other control signals and convert these signals directly into a 12-bit digital value. device input channels a/d channel select bits input pins ht?5f?n 1? acs?~acs0 an0~an13 ht?5fh?n 13 acs?~acs0 an0~an8? an10~an13 note: the an9 input is not connected to the external pin for the ht45fh4n device. external input channels the accompanying block diagram shows the overall internal structure of the a/d converter, together with its associated registers.                      
       

            ?   ?? ?  ?   ?  ? ?  ?   ?    ?    - ?   ? ?     ?   ?? ?    ?     ?  ?      ? ? ?? ?   note: the an9 pin is only internally used and is not connected to the external pin. a/d converter structure
rev. 1.30 10? de?e??e? 1?? ?01? rev. 1.30 105 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu a/d converter register description overall operation of the a/d converter is controlled using fve registers. a read only register pair exists to store the adc data 12-bit value. the remaining three registers are control registers which setup the operating and control function of the a/d converter. name bit 7 6 5 4 3 2 1 0 adrl(adrfs=0) d3 d? d1 d0 adrl(adrfs=1) d7 d? d5 d? d3 d? d1 d0 adrh(adrfs=0) d11 d10 d9 d8 d7 d? d5 d? adrh(adrfs=1) d11 d10 d9 d8 adcr0 start eocb adoff adrfs acs3 acs? acs1 acs0 adcr1 acs? vbgen vrefs adck? adck1 adck0 acerl ace7 ace? ace5 ace? ace3 ace? ace1 ace0 acerh ace13 ace1? ace11 ace10 ace9 ace8 a/d converter register list a/d converter data registers C adrl, adrh as the device contains an internal 12-bit a/d converter, it requires two data registers to store the converted value. these are a high byte register, known as adrh, and a low byte register, known as adrl. after the conversion process takes place, these registers can be directly read by the microcontroller to obtain the digitised conversion value. as only 12 bits of the 16-bit register space is utilised, the format in which the data is stored is controlled by the adrfs bit in the adcr0 register as shown in the accompanying table. d0~d11 are the a/d conversion result data bits. any unused bits will be read as zero. adrfs adrh adrl 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 d11 d10 d9 d8 d7 d? d5 d? d3 d? d1 d0 0 0 0 0 1 0 0 0 0 d11 d10 d9 d8 d7 d? d5 d? d3 d? d1 d0 a/d data registers a/d converter control registers C adcr0, adcr1, acerl, acerh to control the function and operation of the a/d converter, three control registers known as adcr0, adcr1, acerl and acerh are provided. these 8-bit registers defne functions such as the selection of which analog channel is connected to the internal a/d converter, the digitised data format, the a/d clock source as well as controlling the start function and monitoring the a/d converter end of conversion status. the acs3~acs0 bits in the adcr0 register and acs4 bit is the adcr1 register defne the adc input channel number. as the device contains only one actual analog to digital converter hardware circuit, each of the individual 14 analog inputs must be routed to the converter. it is the function of the acs4 ~ acs0 bits to determine which analog channel input signals or internal 1.25v is actually connected to the internal a/d converter. the acerl and acerh control registers contain the acer13~acer0 bits which determine which pins on port a are used as analog inputs for the a/d converter input and which pins are not to be used as the a/d converter input. setting the corresponding bit high will select the a/d input function, clearing the bit to zero will select either the i/o or other pin-shared function. when the pin is selected to be an a/d input, its original function whether it is an i/o or other pin-shared function will be removed. in addition, any internal pull-high resistors connected to these pins will be automatically removed if the pin is selected to be an a/d input.
rev. 1.30 10? de?e??e? 1?? ?01? rev. 1.30 107 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu adcr0 register bit 7 6 5 4 3 2 1 0 na?e start eocb adoff adrfs acs3 acs? acs1 acs0 r/w r/w r r/w r/w r/w r/w r/w r/w por 0 1 1 0 0 0 0 0 bit 7 start : start the a/d conversion 010: start 01: reset the a/d converter and set eocb to 1 this bit is used to initiate an a/d conversion process. the bit is normally low but if set high and then cleared low again, the a/d converter will initiate a conversion process. when the bit is set high the a/d converter will be reset. bit 6 eocb : end of a/d conversion fag 0: a/d conversion ended 1: a/d conversion in progress this read only fag is used to indicate when an a/d conversion process has completed. when the conversion process is running the bit will be high. bit 5 adoff : adc module power on/off control bit 0: adc module power on 1: adc module power off this bit controls the power to the a/d internal function. this bit should be cleared to zero to enable the a/d converter. if the bit is set high then the a/d converter will be switched off reducing the device power consumption. as the a/d converter will consume a limited amount of power, even when not executing a conversion, this may be an important consideration in power sensitive battery powered applications. note: 1. it is recommended to set adoff=1 before entering idle/sleep mode for saving power. 2. adoff=1 will power down the adc module. bit 4 adrfs : adc data format control 0: adc data msb is adrh bit 7, lsb is adrl bit 4 1: adc data msb is adrh bit 3, lsb is adrl bit 0 this bit controls the format of the 12-bit converted a/d value in the two a/d data registers. details are provided in the a/d data register section. bit 3 ~ 0 acs3 ~ acs0 : select a/d channel (when acs4 is 0) 0000: an0 0001: an1 0010: an2 0011: an3 0100: an4 0101: an5 0110: an6 0111: an7 1000: an8 1001: an9 C only available for the HT45F4N device 1010: an10 1011: an11 1100: an12 1101: an13 1110: an14 ( from opa output for ocp 0 ) 1111: an15 ( from opa output for ocp 1 ) these are the a/d channel select control bits. as there is only one internal hardware a/d converter each of the eight a/d inputs must be routed to the internal converter using these bits. if bit acs4 in the adcr1 register is set high then the internal 1.25v will be routed to the a/d converter.
rev. 1.30 10? de?e??e? 1?? ?01? rev. 1.30 107 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu adcr1 register bit 7 6 5 4 3 2 1 0 na?e acs? vbgen vrefs adck? adck1 adck0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7 acs4 : select internal 1.25v as adc input control 0: disable 1: enable this bit enables 1.25v to be connected to the a/d converter. the vbgen bit must frst have been set to enable the bandgap circuit 1.25v voltage to be used by the a/d converter. when the acs4 bit is set high, the bandgap 1.25v voltage will be routed to the a/d converter and the other a/d input channels disconnected. bit 6 vbgen : internal 1.25v control 0: disable 1: enable this bit controls the internal bandgap circuit on/off function to the a/d converter. when the bit is set high the bandgap 1.25v voltage can be used by the a/d converter. if 1.25v is not used by the a/d converter and the lvr/lvd function is disabled then the bandgap reference circuit will be automatically switched off to conserve power. when 1.25v is switched on for use by the a/d converter, a time t bg should be allowed for the bandgap circuit to stabilise before implementing an a/d conversion. bit 5 unimplemented, read as 0 bit 4 vrefs : select adc reference voltage 0: internal adc power 1: vref pin this bit is used to select the reference voltage for the a/d converter. if the bit is high then the a/d converter reference voltage is supplied on the external vref pin. if the pin is low then the internal reference is used which is taken from the power supply pin vdd. bit 3 unimplemented, read as 0 bit 2 ~ 0 adck2 ~ adck0 : select adc clock source 000: f 001: f /2 010: f /4 011: f /8 100: f /16 101: f /32 110: f /64 111: undefned these three bits are used to select the clock source for the a/d converter.
rev. 1.30 108 de?e??e? 1?? ?01? rev. 1.30 109 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu acerl register bit 7 6 5 4 3 2 1 0 na?e ace7 ace? ace5 ace? ace3 ace? ace1 ace0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 bit 7 ace7 : defne pc2 is ouvp02, a/d input or not 0: not ouvp02 and not a/d input 1:ouvp02 or (and) a/d input, an7 bit 6 ace6 : defne pc1 is ouvp01, a/d input or not 0: not ouvp01 and not a/d input 1: ouvp01 or (and) a/d input, an6 bit 5 ace5 : defne pc0 is ouvp00, a/d input or not 0: not ouvp00 and not a/d input 1: ouvp00 or (and) a/d input, an5 bit 4 ace4 : defne pa7 is a/d input or not 0: not a/d input 1: a/d input, an4 bit 3 ace3 : defne pa6 is a/d input or not 0: not a/d input 1: a/d input, an3 bit 2 ace2 : defne pa2 is a/d input or not 0: not a/d input 1: a/d input, an2 bit 1 ace1 : defne pa1 is a/d input or not 0: not a/d input 1: a/d input, an1 bit 0 ace0 : defne pa0 is a/d input or not 0: not a/d input 1: a/d input, an0
rev. 1.30 108 de?e??e? 1?? ?01? rev. 1.30 109 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu acerh register bit 7 6 5 4 3 2 1 0 na?e ace13 ace1? ace11 ace10 ace9 ace8 r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 bit 7~6 unimplemented, read as 0 bit 5 ace13 : defne pd5 is a/d input or not 0: not a/d input 1: a/d input, an13 bit 4 ace12 : defne pd4 is a/d input or not 0: not a/d input 1: a/d input, an12 bit 3 ace11 : defne pd3 is a/d input or not 0: not a/d input 1: a/d input, an11 bit 2 ace10 : defne pd2 is a/d input or not 0: not a/d input 1: a/d input, an10 bit 1 ace9 : defne pd1 is a/d input or not 0: not a/d input 1: a/d input, an9 note that the an9 is not connected to the external pin for the ht45fh4n device. bit 0 ace8 : defne pd0 is a/d input or not 0: not a/d input 1: a/d input, an8
rev. 1.30 110 de?e??e? 1?? ?01? rev. 1.30 111 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu a/d operation the start bit in the adcr0 register is used to start and reset the a/d converter. when the microcontroller sets this bit from low to high and then low again, an analog to digital conversion cycle will be initiated. when the start bit is brought from low to high but not low again, the eocb bit in the adcr0 register will be set high and the analog to digital converter will be reset. it is the start bit that is used to control the overall start operation of the internal analog to digital converter. the eocb bit in the adcr0 register is used to indicate when the analog to digital conversion process is complete. this bit will be automatically cleared to 0 by the microcontroller after a conversion cycle has ended. in addition, the corresponding a/d interrupt request fag will be set in the interrupt control register, and if the interrupts are enabled, an appropriate internal interrupt signal will be generated. this a/d internal interrupt signal will direct the program flow to the associated a/d internal interrupt address for processing. if the a/d internal interrupt is disabled, the microcontroller can be used to poll the eocb bit in the adcr0 register to check whether it has been cleared as an alternative method of detecting the end of an a/d conversion cycle. the clock source for the a/d converter, which originates from the system clock f sys , can be chosen to be either f sys or a subdivided version of f sys . the division ratio value is determined by the adck2~adck0 bits in the adcr1 register. although the a/d clock source is determined by the system clock f sys , and by bits adck2~adck0, there are some limitations on the maximum a/d clock source speed that can be selected. as the recommended range of permissible a/d clock period, t adck , is from 0.5s to 10 s, care must be taken for system clock frequencies. for example, if the system clock operates at a frequency of 4mhz, the adck2~adck0 bits should not be set to 000b or 110b . doing so will give a/d clock periods that are less than the minimum a/d clock period or greater than the maximum a/d clock period which may result in inaccurate a/d conversion values. refer to the following table for examples, where values marked with an asterisk * show where, depending upon the device, special care must be taken, as the values may be less than the specifed minimum a/d clock period. f sys a/d clock period (t ad ck ) adck2, adck1, adck0 =000 (f sys ) adck2, adck1, adck0 =001 (f sys /2) adck2, adck1, adck0 =010 (f sys /4) adck2, adck1, adck0 =011 (f sys /8) adck2, adck1, adck0 =100 (f sys /16) adck2, adck1, adck0 =101 (f sys /32) adck2, adck1, adck0 =110 (f sys /64) adck2, adck1, adck0 =111 1mhz 1s 2s 4s 8s 16s* 32s* 64s* undefned ?mhz 500ns 1s 2s 4s 8s 16s* 32s* undefned ?mhz 250ns* 500ns 1s 2s 4s 8s 16s* undefned 8mhz 125ns* 250ns* 500ns 1s 2s 4s 8s undefned 1?mhz 83ns* 167ns* 333ns* ??7ns 1.33s 2.67s 5.33s undefned a/d clock period examples
rev. 1.30 110 de?e??e? 1?? ?01? rev. 1.30 111 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu controlling the power on/off function of the a/d converter circuitry is implemented using the adoff bit in the adcr0 register. this bit must be zero to power on the a/d converter. when the adoff bit is cleared to zero to power on the a/d converter internal circuitry a certain delay, as indicated in the timing diagram, must be allowed before an a/d conversion is initiated. even if no pins are selected for use as a/d inputs by clearing the ace13~ace0 bits in the acerl and acerh registers, if the adoff bit is zero then some power will still be consumed. in power conscious applications it is therefore recommended that the adoff is set high to reduce power consumption when the a/d converter function is not being used. the reference voltage supply to the a/d converter can be supplied from either the positive power supply pin, vdd, or from an external reference sources supplied on pin vref. the desired selection is made using the vrefs bit. as the vref pin is pin-shared with other functions, when the vrefs bit is set high, the vref pin function will be selected and the other pin functions will be disabled automatically. a/d input pins all of the a/d analog input pins are pin-shared with the i/o pins as well as other functions. the ace 13 ~ace0 bits in the acerl and acerh registers, determine whether the input pins are setup as a/d converter analog inputs or whether they have other functions. if the ace 13 ~ace0 bits for its corresponding pin is set high then the pin will be setup to be an a/d converter input and the original pin functions disabled. in this way, pins can be changed under program control to change their function between a/d inputs and other functions. all pull-high resistors, which are setup through register programming, will be automatically disconnected if the pins are setup as a/ d inputs. note that it is not necessary to frst setup the a/d pin as an input in the pac port control register to enable the a/d input as when the ace 13 ~ace0 bits enable an a/d input, the status of the port control register will be overridden. note that the a/d input, an9, is not connected to the external pin for the ht45fh4n device. the a/d converter has its own reference voltage pin, vref, however the reference voltage can also be supplied from the power supply pin, a choice which is made through the vrefs bit in the adcr1 register. the analog input values must not be allowed to exceed the value of v ref .                     
            ?   ?    ?    ? ?    ? ? - a/d input structure
rev. 1.30 11 ? de?e??e? 1?? ?01? rev. 1.30 113 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu summary of a/d conversion steps the following summarises the individual steps that should be executed in order to implement an a/ d conversion process. ? step 1 select the required a/d conversion clock by correctly programming bits adck2~adck0 in the adcr1 register. ? step 2 enable the a/d by clearing the adoff bit in the adcr0 register to zero. ? step 3 select which channel is to be connected to the internal a/d converter by correctly programming the acs4~acs0 bits which are also contained in the adcr1 and adcr0 register. ? step 4 select which pins are to be used as a/d inputs and confgure them by correctly programming the ace13~ace0 bits in the acerl and acerh register. ? step 5 if the interrupts are to be used, the interrupt control registers must be correctly configured to ensure the a/d converter interrupt function is active. the master interrupt control bit, emi, and the a/d converter interrupt bit, ade, must both be set high to do this. ? step 6 the analog to digital conversion process can now be initialised by setting the start bit in the adcr0 register from low to high and then low again. note that this bit should have been originally cleared to zero. ? step 7 to check when the analog to digital conversion process is complete, the eocb bit in the adcr0 register can be polled. the conversion process is complete when this bit goes low. when this occurs the a/d data registers adrl and adrh can be read to obtain the conversion value. as an alternative method, if the interrupts are enabled and the stack is not full, the program can wait for an a/d interrupt to occur. note: when checking for the end of the conversion process, if the method of polling the eocb bit in the adcr0 register is used, the interrupt enable step above can be omitted. the accompanying diagram shows graphically the various stages involved in an analog to digital conversion process and its associated timing. after an a/d conversion process has been initiated by the application program, the microcontroller internal hardware will begin to carry out the conversion, during which time the program can continue with other functions. the time taken for the a/d conversion is 16 t adck where t adck is equal to the a/d clock period.
rev. 1.30 11 ? de?e??e? 1?? ?01? rev. 1.30 113 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu               
            
                  ?? ?   ?  ?   ??? ? ? ? ?  ?                      ?  ? ?         ?                     ?                  
           ?  ? ?           - ?                ? ?   ? ??  - a/d conversion timing programming considerations during microcontroller operations where the a/d converter is not being used, the a/d internal circuitry can be switched off to reduce power consumption, by setting bit adoff high in the adcr0 register. when this happens, the internal a/d converter circuits will not consume power irrespective of what analog voltage is applied to their input lines. if the a/d converter input lines are used as normal i/os, then care must be taken as if the input voltage is not at a valid logic level, then this may lead to some increase in power consumption. a/d transfer function as the device contain s a 12-bit a/d converter, its full-scale converted digitised value is equal to fffh. since the full-scale analog input value is equal to the v dd or v ref voltage, this gives a single bit analog input value of v dd or v ref divided by 4096. 1 lsb= (v dd or v ref ) / 4096 the a/d converter input voltage value can be calculated using the following equation: a/d input voltage = a/d output digital value (v dd or v ref ) / 4096 the diagram shows the ideal transfer function between the analog input value and the digitised output value for the a/d converter. except for the digitised zero value, the subsequent digitised values will change at a point 0.5 lsb below where they would change without the offset, and the last full scale digitised value will change at a point 1.5 lsb below the v dd or v ref level.                



   
 
 
 
 
 ?  ? ? ? ?  ? ??     ?   ?   
 ? ideal a/d transfer function
rev. 1.30 11 ? de?e??e? 1?? ?01? rev. 1.30 115 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu a/d programming examples the following two programming examples illustrate how to setup and implement an a/d conversion. in the frst example, the method of polling the eocb bit in the adcr0 register is used to detect when the conversion cycle is complete, whereas in the second example, the a/d interrupt is used to determine when the conversion is complete. example: using an eocb polling method to detect the end of conversion clr ade ; disable adc interrupt mov a,03h mov adcr1,a ; select f sys /8 as a/d clock and switch off 1.25v clr adoff mov a,0fh ; setup acerl to confgure pins an0~an3 mov acerl,a mov a, 00h mov acerh, a mov a,0 1 h mov adcr0,a ; enable and connect an0 channel to a/d converter : start_conversion: clr start ; high pulse on start bit to initiate conversion set start ; reset a/d clr start ; start a/d polling_eoc: sz eocb ; poll the adcr0 register eocb bit to detect end of a/d conversion jmp polling_eoc ; continue polling mov a,adrl ; read low byte conversion result value mov adrl_buffer,a ; save result to user defned register mov a,adrh ; read high byte conversion result value mov adrh_buffer,a ; save result to user defned register : : jmp start_conversion ; start next a/d conversion
rev. 1.30 11 ? de?e??e? 1?? ?01? rev. 1.30 115 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu example: using the interrupt method to detect the end of conversion clr ade ; disable adc interrupt mov a,03h mov adcr1,a ; select f sys /8 as a/d clock and switch off 1.25v clr adoff mov a,0fh ; setup acerl to confgure pins an0~an3 mov acerl,a mov a, 00h mov acerh, a mov a,0 1 h mov adcr0,a ; enable and connect an0 channel to a/d converter start_conversion: clr start ; high pulse on start bit to initiate conversion set start ; reset a/d clr start ; start a/d clr adf ; clear adc interrupt request fag set ade ; enable adc interrupt set emi ; enable global interrupt : : ; adc interrupt service routine adc_isr: mov acc_stack,a ; save acc to user defned memory mov a,status mov status_stack,a ; save status to user defned memory : : mov a,adrl ; read low byte conversion result value mov adrl_buffer,a ; save result to user defned register mov a,adrh ; read high byte conversion result value mov adrh_buffer,a ; save result to user defned register : : exit_int_isr: mov a,status_stack mov status,a ; restore status from user defned memory mov a,acc_stack ; restore acc from user defned memory reti
rev. 1.30 11 ? de?e??e? 1?? ?01? rev. 1.30 117 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu complementary pwm output the device provides a complementary output pair of signals which can be used as a pwm driver signal. the signal is sourced from the tm1 output signal, tp1 or the tm2 output signal, tp2. for pmos type upper side driving, the pwm output is an active low signal while for nmos type lower side driving the pwm output is an active high signal. when these complementary pwm outputs are both used to drive the upper and low sides, the dead time generator will automatically be enabled and a dead time, which is programmable using the dtpscn and dtn bits in the cprn register, will be inserted to prevent excessive dc currents. the dead time will be inserted whenever the rising edge of the dead time generator input signal occurs. with a dead time insertion, the output signals are eventually sent out to the external power transistors. the dead time generator will only be enabled if both of the complementary outputs are used, as determined by the outncp bits in the tmpc register. tp1 or tp2 dead time generator dtpscn [1:0] prescaler f h a b dtn [2:0] e c d pwmnh (driving upper side pmos, active low) pwmnl (driving lower side nmos, active high) f d outncp [1:0] complementary pwm output block diagram tp1 or tp2 a b c d e dead time dead time dead time dead time dead time dead time complementary pwm output waveform
rev. 1.30 11 ? de?e??e? 1?? ?01? rev. 1.30 117 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu cpr0 register bit 7 6 5 4 3 2 1 0 na?e dtpsc01 dtpsc00 dt0? dt01 dt00 r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 bit 7 ~ 5 unimplemented, read as 0 bit 4 ~ 3 dtpsc01~dtpsc00 : dead time prescaler division ratio select 00: f h /1 01: f h /2 10: f h /4 11: f h /8 bit 2 ~ 0 dt02~dt00 : dead time select 000: dead time is [(1/f )-(1/f h )] ~ (1/f ) 001: dead time is [(2/f )-(1/f h )] ~ (2/f ) 010: dead time is [(3/f )-(1/f h )] ~ (3/f ) 011: dead time is [(4/f )-(1/f h )] ~ (4/f ) 100: dead time is [(5/f )-(1/f h )] ~ (5/f ) 101: dead time is [(6/f )-(1/f h )] ~ (6/f ) 110: dead time is [(7/f )-(1/f h )] ~ (7/f ) 111: dead time is [(8/f )-(1/f h )] ~ (8/f ) cpr1 register bit 7 6 5 4 3 2 1 0 na?e dtpsc11 dtpsc10 dt1? dt11 dt10 r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 bit 7 ~ 5 unimplemented, read as 0 bit 4 ~ 3 dtpsc11~dtpsc10 : dead time prescaler division ratio select 00: f h /1 01: f h /2 10: f h /4 11: f h /8 bit 2 ~ 0 dt12~dt10 : dead time select 000: dead time is [(1/f )-(1/f h )] ~ (1/f ) 001: dead time is [(2/f )-(1/f h )] ~ (2/f ) 010: dead time is [(3/f )-(1/f h )] ~ (3/f ) 011: dead time is [(4/f )-(1/f h )] ~ (4/f ) 100: dead time is [(5/f )-(1/f h )] ~ (5/f ) 101: dead time is [(6/f )-(1/f h )] ~ (6/f ) 110: dead time is [(7/f )-(1/f h )] ~ (7/f ) 111: dead time is [(8/f )-(1/f h )] ~ (8/f )
rev. 1.30 118 de?e??e? 1?? ?01? rev. 1.30 119 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu over current protection the device includes an over current protection function which provides a protection mechanism for the battery charge and discharge applications. ocp funciton to prevent the possibility of large battery current and load current, the ocp input voltage from the battery sense resistor is compared with a reference voltage generated by an 8-bit d/a converter. the 8-bit d/a converter power is supplied by the external power pin named dapwr. once the ocp input voltage is greater than the reference voltage, it will force the out0h/out1h and out0l/ out1l signals inactive, i.e., the out0h/out1h signal will be forced into a high state and the out0l/out1l signal will be forced into a low state before the polarity control, to turn the external mos off for over current protection. the out0h/out1h and out0l/out1l signals can be forced to an inactive state when an over current event occurs. if an over current event occurs, the corresponding interrupt will be generated. once the over current condition has disappeared, the out0h/out1h and out0l/out1l signals will recover to drive the pwm output. the operational amplifer in the over current protection circuitry can be confgured in an inverting or non-inverting opa confguration to sense the battery current when the battery is undergoing a charge or discharge operation. it is recommended that the opa should be in a non-inverting mode during a charge operation and in an inverting mode during a discharge operation. more information for the outnh and outnl signal polarity and output control is described in the tmpcn register. ocp circuit operation ocp is abbreviation of over current protects circuit. ocp detect input voltage which is proportional to the monitored source current; if the input voltage is larger than reference voltage set by dac, ocp will issue an output signal indicate the source current is over specifcation. 8 ?it dac c ocpnda filte? filte? ?lo?k to adc r 1 r ? a ( r 1 = ?0k ) g = 1 / 5 / 10/ 15/ ?0 ocp 0 o s 1 s 0 s ? s 3 ocpng ? ~ ocpng 0 ocpnf ? ~ ocpnf 0 f flt = f h / ? ocpnm 1 ? ocpnm 0 ocp input over current protection block diagram (n=0 or 1)
rev. 1.30 118 de?e??e? 1?? ?01? rev. 1.30 119 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu t he source voltage is input from ocpn0 or ocpn1. a fter this, four switches s0~s3 consist of a mode select function. an opamp and two resistors consist of a pga function; pga gain can be positive or negative determine by input voltage connect to positive input or negative input of pga. dac is used to generate reference voltage. t he c omparator compares the reference voltage and the amplifed input voltage to produce comparator output fag ( ocp ncx ), fnally flter out ocp ncx to generate ocp n o and ocp interrupt, they are de-bounce version of ocp ncx used to indicates that source current is over specifcation or not. ocp n o is defned as ocp output and ocp interrupt trigger. t he comparator of ocp also has hysteresis function controlled by ocp n chy bit. n ote that the flter clock is f elt =f h /4. t he amplifed input voltage also can be read out by means of another adc from opa output. dac output voltage is controlled by ocpnda register, and the dac output is defne as dac v out = (dac v ref /256) d[7:0] input voltage range t he input voltage can be positive or negative, together with pga operating mode, represent a more fexible application. (1) v in > 0, pga operates in non-inverting mode, the output voltage of pga is vo pga =(1+r 2 /r 1 ) v in (2) for convinced using, when pga operates in non-inverting mode, we provide a unity gain buffer function. i f copnm[1:0]=01 and ocpng[2:0]=000, the pga gain will be 1 and is confgure d as unity gain buffer. t he switches s2 and s3 will be open internally and the output voltage of pga is vo pga =v in (3) 0 > v in >-0.4, pga operates in inverting mode, the output voltage of pga is vo pga =-(r 2 /r 1 ) v in note: if v in is negative , it should not lower than (-0.4v) to avoid leakage current. ocp register overall operation of the over current protection is controlled using several registers. register name bit 7 6 5 4 3 2 1 0 ocp0c0 ocp0m1 ocp0m0 ocp0pc1 ocp0pc0 ocp01len ocp01hen ocp00len ocp00hen ocp0c1 ocp0o ocp0chy ocp0g? ocp0g1 ocp0g0 ocp0f? ocp0f1 ocp0f0 ocp0da d7 d? d5 d? d3 d? d1 d0 a0cal a0ofm a0rs a0of5 a0of? a0of3 a0of? a0of1 a0of0 c0cal ocp0cx c0ofm c0rs c0of? c0of3 c0of? c0of1 c0of0 ocp1c0 ocp1m1 ocp1m0 ocp1pc1 ocp1pc0 ocp11len ocp11hen ocp10len ocp10hen ocp1c1 ocp1o ocp1chy ocp1g? ocp1g1 ocp1g0 ocp1f? ocp1f1 ocp1f0 ocp1da d7 d? d5 d? d3 d? d1 d0 a1cal a1ofm a1rs a1of5 a1of? a1of3 a1of? a1of1 a1of0 c1cal ocp1cx c1ofm c1rs c1of? c1of3 c1of? c1of1 c1of0 ocppc ocp1rv ocp0rv ocp11c ocp10c ocp01c ocp00c ocp register list
rev. 1.30 1?0 de?e??e? 1?? ?01? rev. 1.30 1?1 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu ocppc register bit 7 6 5 4 3 2 1 0 na?e ocp1rv ocp0rv ocp11c ocp10c ocp01c ocp00c r/w r/w r/w r/w r/w r/w r/w por 0 0 1 1 1 1 bit 7~6 unimplemented, read as 0 bit 5 ocp1rv : select ocp1 dac reference voltage 0: avdd pin 1: dapwr pin ocp0rv : select ocp0 dac reference voltage 0: avdd pin 1: dapwr pin bit3 ocp11c : defne pc6 is ocp11 input or not 0: not ocp11 input 1: analog input, ocp11 bit 2 ocp10c : defne pc5 is ocp10 input or not 0: not ocp10 input 1: analog input, ocp10 bit 1 ocp01c : defne pc4 is ocp01 input or not 0: not ocp01 input 1: analog input, ocp01 bit 0 ocp00c : defne pc3 is ocp00 input or not 0: not ocp00 input 1: analog input, ocp00
rev. 1.30 1?0 de?e??e? 1?? ?01? rev. 1.30 1?1 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu ocp0c0 register bit 7 6 5 4 3 2 1 0 na?e ocp0m1 ocp0m0 ocp0pc1 ocp0pc0 ocp01len ocp01hen ocp00len ocp00hen r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 ocp0m1~ocp0m0 : over current protection function 0 operating mode selection 00: ocp 0 disable, s1, s3 on, s0, s2 off 01: ocp 0 enable in non-inverter mode, s0, s3 on, s1, s2 off 10: ocp 0 enable in inverter mode, s1, s2 on, s0, s3 off 11: ocp 0 enable in internal 0v input mode, s1, s3 on, s0, s2 off bit 5~4 ocp0pc1~ocp0pc0 : over current protection 0 pin control 00: ocp0 input is disabled 01: ocp0 input is disabled 10: ocp00 pin is used to as ocp0 input 11: ocp01 pin is used to as ocp0 input bit 3 ocp01len : out1l over current protection 0 enable control 0: disable 1: enable this bit is used to control whether the out1l signal is forced into an inactive state when an over current condition occurs. bit 2 ocp01hen : out1h over current protection 0 enable control 0: disable 1: enable this bit is used to control whether the out1h signal is forced into an inactive state when an over current condition occurs bit 1 ocp00len : out0l over current protection 0 enable control 0: disable 1: enable this bit is used to control whether the out0l signal is forced into an inactive state when an over current condition occurs. bit 0 ocp00hen : out0h over current protection 0 enable control 0: disable 1: enable this bit is used to control whether the out0h signal is forced into an inactive state when an over current condition occurs.
rev. 1.30 1?? de?e??e? 1?? ?01? rev. 1.30 1?3 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu ocp0c1 register bit 7 6 5 4 3 2 1 0 na?e ocp0o ocp0chy ocp0g? ocp0g1 ocp0g0 ocp0f? ocp0f1 ocp0f0 r/w r r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 ocp0o : over current protection 0 comparator filter digital output 0: the monitored source current is not over 1: the monitored source current is over bit 6 ocp0chy : over current protection 0 comparator hysteresis enable control 0: disable 1: enable bit 5~3 ocp0g2~ocp0g0 : over current protection 0 opa gain selection 000: 1 001: 5 010: 10 011: 15 100: 20 101: 20 110: 20 111: 20 bit 2~0 ocp0f2~ocp0f0 : over current protection 0 demodulation flter selection 000: 0 t flt (without flter) 001: 1~2 t flt 010: 3~4 t flt 011: 7~8 t flt 100: 15~16 t flt 101: 31~32 t flt 110: 63~64 t flt 111: 127~128 t flt note: f flt h /4 , flt =1/f flt ocp0da register bit 7 6 5 4 3 2 1 0 na?e d7 d? d5 d? d3 d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 ocp 0 dac data register bit 7 ~ bit 0 8-bit dac data bits. ocp 0 dac output = (dac reference voltage) (dac.7~0)/256
rev. 1.30 1?? de?e??e? 1?? ?01? rev. 1.30 1?3 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu a0cal register bit 7 6 5 4 3 2 1 0 na?e a0ofm a0rs a0of5 a0of? a0of3 a0of? a0of1 a0of0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 1 0 0 0 0 0 bit 7 a0ofm : over current protection 0 operational amplifier input offset voltage cancellation mode select 0: operational amplifer mode 1: input offset voltage cancellation mode note: only if the bits ocp0m1~ocp0m0=11 and a0ofm=1 and c0ofm=0, it can enter into the over current protection 0 operational amplifer input offset voltage cancellation mode. bit 6 a0rs : over current protection 0 operational amplifer offset voltage cancellation reference input select 0: operational amplifer negative input selected 1: operational amplifer positive input selected bit 5~0 a0of5~a0of0 : over current protection 0 operational amplifier input voltage offset cancellation setting c0cal register bit 7 6 5 4 3 2 1 0 na?e ocp0cx c0ofm c0rs c0of? c0of3 c0of? c0of1 c0of0 r/w r r/w r/w r/w r/w r/w r/w r/w por 0 0 1 0 0 0 0 bit 7 ocp0cx : over current protection 0 comparator or operational amplifier digital output for input offset voltage cancellation mode 0: positive input voltage < negative input voltage 1: positive input voltage > negative input voltagel bit 6 c0ofm : over current protection 0 comparator input offset voltage cancellation mode select 0: comparator mode 1: input offset voltage cancellation mode note: only if the bits ocp0m1~ocp0m0=11 and a0ofm=0 and c0ofm=1, it can enter into the over current protection 0 comparator input offset voltage cancellation mode. bit 5 c0rs : over current protection 0 comparator offset voltage cancellation reference input select 0: comparator negative input selected 1: comparator positive input selected bit 4~0 c0of4~c0of0 : over current protection 0 comparator input voltage offset cancellation setting
rev. 1.30 1?? de?e??e? 1?? ?01? rev. 1.30 1?5 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu ocp1c0 register bit 7 6 5 4 3 2 1 0 na?e ocp1m1 ocp1m0 ocp1pc1 ocp1pc0 ocp11len ocp11hen ocp10len ocp10hen r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 ocp1m1~ocp1m0 : over current protection function 1 operating mode selection 00: ocp 1 disable, s1, s3 on, s0, s2 off 01: ocp 1 enable in non-inverter mode, s0, s3 on, s1, s2 off 10: ocp 1 enable in inverter mode, s1, s2 on, s0, s3 off 11: ocp 1 enable in internal 0v input mode, s1, s3 on, s0, s2 off bit 5~4 ocp1pc1~ocp1pc0 : over current protection 1 pin control 00: ocp1 input is disabled 01: ocp1 input is disabled 10: ocp10 pin is used to as ocp1 input 11: ocp11 pin is used to as ocp1 input bit 3 ocp11len : out1l over current protection 1 enable control 0: disable 1: enable this bit is used to control whether the out1l signal is forced into an inactive state when an over current condition occurs. bit 2 ocp11hen : out1h over current protection 1 enable control 0: disable 1: enable this bit is used to control whether the out1h signal is forced into an inactive state when an over current condition occurs bit 1 ocp10len : out0l over current protection 1 enable control 0: disable 1: enable this bit is used to control whether the out0l signal is forced into an inactive state when an over current condition occurs. bit 0 ocp00hen : out0h over current protection 1 enable control 0: disable 1: enable this bit is used to control whether the out0h signal is forced into an inactive state when an over current condition occurs.
rev. 1.30 1?? de?e??e? 1?? ?01? rev. 1.30 1?5 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu ocp1c1 register bit 7 6 5 4 3 2 1 0 na?e ocp1o ocp1chy ocp1g? ocp1g1 ocp1g0 ocp1f? ocp1f1 ocp1f0 r/w r r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 ocp1o : over current protection 1 comparator filter digital output 0: the monitored source current is not over 1: the monitored source current is over bit 6 ocp1chy : over current protection 1 comparator hysteresis enable control 0: disable 1: enable bit 5~3 ocp1g2~ocp1g0 : over current protection 1 opa gain selection 000: 1 001: 5 010: 10 011: 15 100: 20 101: 20 110: 20 111: 20 bit 2~0 ocp1f2~ocp1f0 : over current protection1 demodulation flter selection 000: 0 t flt (without flter) 001: 1~2 t flt 010: 3~4 t flt 011: 7~8 t flt 100: 15~16 t flt 101: 31~32 t flt 110: 63~64 t flt 111: 127~128 t flt note: f flt h /4 , flt =1/f flt ocp1da register bit 7 6 5 4 3 2 1 0 na?e d7 d? d5 d? d3 d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 ocp 1 dac data register bit 7 ~ bit 0 8-bit dac data bits. ocp 1 dac output = (dac reference voltage) (dac.7~0)/256
rev. 1.30 1?? de?e??e? 1?? ?01? rev. 1.30 1?7 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu a1cal register bit 7 6 5 4 3 2 1 0 na?e a1ofm a1rs a1of5 a1of? a1of3 a1of? a1of1 a1of0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 1 0 0 0 0 0 bit 7 a1ofm : over current protection 1 operational amplifier input offset voltage cancellation mode select 0: operational amplifer mode 1: input offset voltage cancellation mode note: only if the bits ocp1m1~ocp1m0=11 and a1ofm=1 and c1ofm=0, it can enter into the over current protection 1 operational amplifer input offset voltage cancellation mode. bit 6 a1rs : over current protection 1 operational amplifer offset voltage cancellation reference input select 0: operational amplifer negative input selected 1: operational amplifer positive input selected bit 5~0 a1of5~a1of0 : over current protection 1 operational amplifier input voltage offset cancellation setting c1cal register bit 7 6 5 4 3 2 1 0 na?e ocp1cx c1ofm c1rs c1of? c1of3 c1of? c1of1 c1of0 r/w r r/w r/w r/w r/w r/w r/w r/w por 0 0 1 0 0 0 0 bit 7 ocp1cx : over current protection 1 comparator or operational amplifier digital output for input offset voltage cancellation mode 0: positive input voltage < negative input voltage 1: positive input voltage > negative input voltagel bit 6 c1ofm : over current protection 1 comparator input offset voltage cancellation mode select 0: comparator mode 1: input offset voltage cancellation mode note: only if the bits ocp1m1~ocp1m0=11 and a1ofm=0 and c1ofm=1, it can enter into the over current protection 1 comparator input offset voltage cancellation mode. bit 5 c1rs : over current protection 1 comparator offset voltage cancellation reference input select 0: comparator negative input selected 1: comparator positive input selected bit 4~0 c1of4~c1of0 : over current protection 1 comparator input voltage offset cancellation setting
rev. 1.30 1?? de?e??e? 1?? ?01? rev. 1.30 1?7 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu offset calibration the ocp circuit has 4 operating modes controlled by ocpnm [1:0], one of it is calibration mode. in calibration mode, op and comparator offset can be calibrated. opamp calibration: step1: set ocpnm [1:0] =11, anofm =1, ocp is now under opamp calibration status step2: set anof [5:0] =000000 then read ocpncx bit step3: let anof[5:0]=anof[5:0]+1 then read ocpncx bit, if ocpncx is changed; record the anof[5:0] data as vos1 step4: set anof [5:0] =111111 then read ocpncx bit step5: let anof[5:0]=anof[5:0]-1 then read ocpncx bit, if ocpncx is changed; record the anof[5:0] data as vos2 step6: restore vos = (vos1 + vos2)/2 to anof[5:0], the calibration is fnished. comparator calibration: step1: set ocpnm[1:0] =11, cnofm =1, ocp is now under comparator calibration status. step2: set cnof [4:0] =00000 then read ocpncx bit step3: let cnof=cnof+1 then read ocpncx bit, if ocpncx is changed; record the cnof[4:0] data as vos1 step4: set cnof [4:0] =11111 then read ocpncx bit step5: let cnof[4:0]=cnof[4:0]-1 then read ocpncx bitr, if ocpncx data is changed; record the cnof[4:0] data as vos2. step6: restore vos = (vos1 + vos2)/2 to cnof[4:0], the calibration is fnished. over voltage protection and under voltage protection the device is build-in with the over/under voltage protection which can be used for the application of battery charge/discharge. ovp function: to prevent from output voltage greater than 5.4v, the ovp input voltage can be compared with 8 bit reference voltage. once ovp is greater than reference voltage, it will force out0h/out0l, out1h/out1l inactive i.e., the out0h/out1h signal will be forced into a high state and the out0l/out1l signal will be forced into a low state to turn external mos off for protection. uvp function: to prevent from output voltage less than 1.0v (external circuit short), the uvp input voltage can be compared with 8 bit reference voltage. once uvp is less than reference voltage, it will force out0h/out0l, out1h/out1l inactive i.e., the out0h/out1h signal will be forced into a high state and the out0l/out1l signal will be forced into a low state to turn external mos off for protection. the out0h/out0l, out1h/out1l can be forced as inactive state for either ovp or uvp occurs. the ovp/uvp also generates interrupt to inform mcu. once ovp/uvp disappears, the out0h/out0l, out1h/out1l will recover to send pwm output. more information for the outnh and outnl signal polarity and output control is described in the tmpcn register.
rev. 1.30 1?8 de?e??e? 1?? ?01? rev. 1.30 1?9 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu 8 - bit dac ovp cmp - + ouvp00 ouvppc1, ouvppc0 debounce ovp interrupt ovplen, ovphen stop dc/dc pwm ovpda[7:0] ovpdb1, ovpdb0 ovpchy ouvp01 ouvp02 ouvppc1, ouvppc0 ouvppc1, ouvppc0 uvp cmp - + debounce uvp interrupt uvplen, uvphen stop dc/dc pwm uvpdb1, uvpdb0 uvpchy 8 - bit dac uvpda[7:0] dac vref dac vref over/under voltage protection block diagram ouvp register overall operation of the voltage protection and under voltage protection is controlled using several registers. register name bit 7 6 5 4 3 2 1 0 ovpda d7 d? d5 d? d3 d? d1 d0 uvpda d7 d? d5 d? d3 d? d1 d0 ouvpc0 ovpcx ouvppc1 ouvppc0 ovpchy ouvprv ovpdb1 ovpdb0 ouvpc1 uvpcx ovpen uvpen uvpchy uvpdb1 uvpdb0 ouvpc? uvp1len uvp1hen uvp0len uvp0hen ovp1len ovp1hen ovp0len ovp0hen ouvp register list ovpda register bit 7 6 5 4 3 2 1 0 na?e d7 d? d5 d? d3 d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 ovp dac data register bit 7 ~ bit 0 8-bit dac data bits. ovp dac output = (dac reference voltage) (dac.7~0)/256 uvpda register bit 7 6 5 4 3 2 1 0 na?e d7 d? d5 d? d3 d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 uvp dac data register bit 7 ~ bit 0 8-bit dac data bits. uvp dac output = (dac reference voltage) (dac.7~0)/256
rev. 1.30 1?8 de?e??e? 1?? ?01? rev. 1.30 1?9 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu ouvpc0 register bit 7 6 5 4 3 2 1 0 na?e ovpcx ouvppc1 ouvppc0 ovpchy ouvprv ovpdb1 ovpdb0 r/w r r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7 ovpcx : over voltage protection comparator digital output 0: positive input voltage < negative input voltage 1: positive input voltage > negative input voltage bit 6~5 ouvppc1~ouvppc0 : over voltage protection and under voltage protection pin control 00: ouvp input is disabled 01: ouvp00 pin is used to as ouvp input 10: ouvp01 pin is used to as ouvp input 11: ouvp02 pin is used to as ouvp input bit 4 ovpchy : over voltage protection comparator hysteresis enable control 0: disable 1: enable bit 3 unimplemented, read as 0 bit 2 ouvprv : select ovp and uvp dac reference voltage 0: avdd pin 1: dapwr pin bit 1~0 ovpdb1~ovpdb0 : over voltage protection comparator debounce time select 00: no debounce 01: debounce time = (7~8) 1/f h 10: debounce time = (15~16) 1/f h 11: debounce time = (31~32) 1/f h ouvpc1 register bit 7 6 5 4 3 2 1 0 na?e uvpcx ovpen uvpen uvpchy uvpdb1 uvpdb0 r/w r r/w r/w r/w r/w r/w por 0 0 0 0 0 bit 7 uvpcx : under voltage protection comparator digital output 0: positive input voltage < negative input voltage 1: positive input voltage > negative input voltage bit 6 ovpen : over voltage protection function enable control 0: disable 1: enable if the ovpen bit is cleared to 0, the over voltage protection function is disabled and no power will be consumed. this results in the comparator and d/a converter of ovp all being switched off. bit 5 uvpen : under voltage protection function enable control 0: disable 1: enable if the uvpen bit is cleared to 0, the under voltage protection function is disabled and no power will be consumed. this results in the comparator and d/a converter of uvp all being switched off. bit 4 uvpchy : under voltage protection comparator hysteresis enable control 0: disable 1: enable bit 3~2 unimplemented, read as 0
rev. 1.30 130 de?e??e? 1?? ?01? rev. 1.30 131 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu bit 1~0 uvpdb1~uvpdb0 : under voltage protection comparator debounce time select 00: no debounce 01: debounce time = (7~8) 1/f h 10: debounce time = (15~16) 1/f h 11: debounce time = (31~32) 1/f h ouvpc2 register bit 7 6 5 4 3 2 1 0 na?e uvp1len uvp1hen uvp0len uvp0hen ovp1len ovp1hen ovp0len ovp0hen r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 uvp1len : out1l under voltage protection enable control 0: disable 1: enable this bit is used to control whether the out1l signal is forced into an inactive state when an over voltage condition occurs. bit 6 uvp1hen : out1h under voltage protection enable control 0: disable 1: enable this bit is used to control whether the out1h signal is forced into an inactive state when an over voltage condition occurs. bit 5 uvp0len : out0l under voltage protection enable control 0: disable 1: enable this bit is used to control whether the out0l signal is forced into an inactive state when an over voltage condition occurs. bit 4 uvp0hen : out0h under voltage protection enable control 0: disable 1: enable this bit is used to control whether the out0h signal is forced into an inactive state when an over voltage condition occurs. bit 3 ovp1len : out1l over voltage protection enable control 0: disable 1: enable this bit is used to control whether the out1l signal is forced into an inactive state when an over voltage condition occurs. bit 2 ovp1hen : out1h over voltage protection enable control 0: disable 1: enable this bit is used to control whether the out1h signal is forced into an inactive state when an over voltage condition occurs. bit 1 ovp0len : out0l over voltage protection enable control 0: disable 1: enable this bit is used to control whether the out0l signal is forced into an inactive state when an over voltage condition occurs. bit 0 ovp0hen : out0h over voltage protection enable control 0: disable 1: enable this bit is used to control whether the out0h signal is forced into an inactive state when an over voltage condition occurs.
rev. 1.30 130 de?e??e? 1?? ?01? rev. 1.30 131 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu usb charge/discharge auto detection the device includes three usb ports named d0+/d0-, d1+/d1- and d2+/d2- to implement the charge/discharge auto detection functions. users can distinguish the device connected to the usb ports is a dedicated charger, portable device, general usb interface or charging device with usb interface by monitoring the voltage and current of the connected usb lines. usb0 the usb0 port is used to connect to a dedicated charger port to charge this device with a specifc voltage and current. the d0+ line can output a voltage, v dp_src , with a value of 0.6v, which is enabled by setting the vdpon bit of aduc0 register and switched on by setting the d0ps bit in the aduc1 register. if the d0ps bit is set to 1 to select the v dp_src voltage to be output, the corresponding i/o pin function will automatically be disabled by hardware. when this port is connected to a dedicated charger, the 0.6v voltage can be output on the d0+ line and then measured on the d0- line by the a/d converter. the usb0 lines, d0+ and d0-, are pin-shared with normal i/ o function and a/d function determined by the ace8 and ace9 bits respectively in the acerh register. both the d0+ and d0- lines are internally connected a pull low resistor to vss which is controlled by the d0npl and d0ppl bits in the aduc2 register. it is important to note that the analog function has higher priority than digital functions when the analog and digital functions are implemented on the same pin. ht45fh4n d0+ pd0 an8 ace8 v dp_src d0ps d0- an9 a/d converter dedicated charger / charging host pd1 ace9 d+ d- note: the d0- is only internally used and is not connected to the external pin for the ht45fh4n device. usb0 connection diagram
rev. 1.30 13? de?e??e? 1?? ?01? rev. 1.30 133 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu usb1, usb2 the usb1 and usb2 ports are used to connect to portable devices to supply power with a specifc voltage and current. the usb1 and usb2 lines, d1+ /d1- and d2+ /d2-, are pin-shared with normal i/o function, a/d function and d/a function determined by the ace10~ace13 bits, d1ns/ d1ps and d2ns/d2ps bits respectively. there is an analog switch connected between the d1+ and d1- lines, which is controlled by the usw1 bit. similarly, there is an analog switch connected between the d2+ and d2- lines, which is controlled by the usw2 bit. when the usw1 or usw2 bit is set to 1 to internally connect the d1+ /d1- or d2+ /d2- lines, the usb1, usb2 functions and the output function of the i/o pin shared with the d1- or d2- line will automatically be disabled if the d1+ /d1- or d2+ /d2- lines are both confgured as i/o pin output function. the d1+ /d1- and d2+ / d2- lines are individually connected a pull low resistor to vss respectively which are controlled by the d1npl/d1ppl and d2npl/d2ppl bits in the aduc2 register. it is important to note that the analog function has higher priority than digital functions when the analog and digital functions are implemented on the same pin. ht45fh4n d1+ d1- portable device d+ d- pd2 an10 ace10 dac0 d1ps an11 pd3 ace11 v r a/d usb phy dac1 d1ns usw1 a/d usb1 connection diagram ht45fh4n d2+ d2- portable device d+ d- pd4 an12 ace12 dac0 d2ps an13 pd5 ace13 v r a/d usb phy dac1 d2ns usw2 a/d usb2 connection diagram
rev. 1.30 13? de?e??e? 1?? ?01? rev. 1.30 133 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu usb charge/discharge auto detection registers overall operation of the usb charge/discharge auto detection function is controlled using several registers. register name bit 7 6 5 4 3 2 1 0 aduda0 d7 d? d5 d? d3 d? d1 d0 aduda1 d7 d? d5 d? d3 d? d1 d0 aduc0 vdpon usw? usw1 dac1rv dac0rv dac1on dac0on aduc1 d?ns d?ps d1ns d1ps d0ps aduc? d?npl d?ppl d1npl d1ppl d0npl d0ppl aduda0 register bit 7 6 5 4 3 2 1 0 na?e d7 d? d5 d? d3 d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 dac0 data register bit 7 ~ bit 0 8-bit dac0 data bits. dac0 output = (vdd or dapwr) (aduda0 [7~0]) / 256 aduda1 register bit 7 6 5 4 3 2 1 0 na?e d7 d? d5 d? d3 d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 dac1 data register bit 7 ~ bit 0 8-bit dac1 data bits. dac1 output = (vdd or dapwr) (aduda1 [7~0]) / 256
rev. 1.30 13? de?e??e? 1?? ?01? rev. 1.30 135 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu aduc0 register bit 7 6 5 4 3 2 1 0 na?e vdpon usw? usw1 dac1rv dac0rv dac1on dac0on r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 unimplemented, read as 0 bit 6 vdpon : v dp_src voltage enable control 0: disable 1: enable bit 5 usw2 : usb2 d2+/d2- switch control 0: switch off 1: switch on if this bit is set to 1 to connect the d2+ and d2- lines together, the usb2 function will be disable automatically and the output function of the i/o pin shared with the d2- line will also be disabled if the d2+ and d2- lines are both confgured as i/o pin output function. bit 4 usw1 : usb1 d1+/d1- switch control 0: switch off 1: switch on if this bit is set to 1 to connect the d1+ and d1- lines together, the usb1 function will be disable automatically and the output function of the i/o pin shared with the d1- line will also be disabled if the d1+ and d1- lines are both confgured as i/o pin output function. bit 3 dac1rv : dac1 reference voltage select 0: vdd pin 1: dapwr pin bit 2 dac0rv : dac0 reference voltage select 0: vdd pin 1: dapwr pin bit 1 dac1on : dac1 enable control 0: disable 1: enable bit 0 dac0on : dac0 enable control 0: disable 1: enable
rev. 1.30 13? de?e??e? 1?? ?01? rev. 1.30 135 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu aduc1 register bit 7 6 5 4 3 2 1 0 na?e d?ns d?ps d1ns d1ps d0ps r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5 d2ns : defne d2- is dac1 output or not 0: not dac1 output 1: dac1 output bit 4 d2ps : defne d2+ is dac0 output or not 0: not dac0 output 1: dac0 output bit 3 d1ns : defne d1- is dac1 output or not 0: not dac1 output 1: dac1 output bit 2 d1ps : defne d1+ is dac0 output or not 0: not dac0 output 1: dac0 output bit 1 unimplemented, read as 0 bit 0 d0ps : defne d0+ is v dp_src output or not 0: not v dp_src output 1: v dp_src output aduc2 register bit 7 6 5 4 3 2 1 0 na?e d?npl d?ppl d1npl d1ppl d0npl d0ppl r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5 d2npl : d2- pin pull-low control 0: disable 1: enable bit 4 d2ppl : d2+ pin pull-low control 0: disable 1: enable bit 3 d1npl : d1- pin pull-low control 0: disable 1: enable bit 2 d1ppl : d1+ pin pull-low control 0: disable 1: enable bit 1 d0npl : d0- pin pull-low control 0: disable 1: enable bit 0 d0ppl : d0+ pin pull-low control 0: disable 1: enable
rev. 1.30 13? de?e??e? 1?? ?01? rev. 1.30 137 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu interrupts interrupts are an important part of any microcontroller system. when an external event or an internal function such as a timer module or an a/d converter requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. the device contains several external interrupt and internal interrupts functions. the external interrupt is generated by the action of the external int0, int1 and int2 pins, while the internal interrupts are generated by various internal functions such as the tms, under voltage protection function, over voltage protection function, over current protection functions, time base, lvd, eeprom and the a/d converter. interrupt registers overall interrupt control, which basically means the setting of request flags when certain microcontroller conditions occur and the setting of interrupt enable bits by the application program, is controlled by a series of registers, located in the special purpose data memory, as shown in the accompanying table. the number of registers depends upon the device chosen but fall into three categories. the frst is the intc0~intc3 registers which setup the primary interrupts, the second is the mfi0~mfi3 registers which setup the multi-function interrupts. finally there is an integ register to setup the external interrupt trigger edge type. each register contains a number of enable bits to enable or disable individual registers as well as interrupt flags to indicate the presence of an interrupt request. the naming convention of these follows a specifc pattern. first is listed an abbreviated interrupt type, then the (optional) number of that interrupt followed by either an e for enable/disable bit or f for request fag. function enable bit request flag notes glo?al emi intn pin intne intnf n=0~? ovp ovpe ovpf uvp uvpe uvpf ocpn ocpne ocpnf n=0 o? 1 a/d conve?te? ade adf multi-fun?tion mfne mfnf n=0~3 ti ?e base tbne tbnf n=0 o? 1 lvd lve lvf eeprom dee def tm tnpe tnpf n=0~3 tnae tnaf interrupt register bit naming conventions name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 integ int?s1 int?s0 int1s1 int1s0 int0s1 int0s0 intc0 ocp0f ovpf ocp1f ocp0e ovpe ocp1e emi intc1 int?f int1f int0f uvpf int?e int1e int0e uvpe intc? mf3f mf?f mf1f mf0f mf3e mf?e mf1e mf0e intc3 lvf tb1f tb0f adf lve tb1e tb0e ade mfi0 def t0af t0pf dee t0ae t0pe mfi1 t1af t1pf t1ae t1pe mfi? t?af t?pf t?ae t?pe mfi3 t3af t3pf t3ae t3pe interrupt register contents
rev. 1.30 13? de?e??e? 1?? ?01? rev. 1.30 137 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu integ register bit 7 6 5 4 3 2 1 0 na?e int?s1 int?s0 int1s1 int1s0 int0s1 int0s0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7 ~ 6 unimplemented, read as 0 bit 5 ~ 4 int2s1, int2s0 : defnes int2 interrupt active edge 00: disabled interrupt 01: rising edge interrupt 10: falling edge interrupt 11: dual edge interrupt bit 3 ~ 2 int1s1, int1s0 : defnes int1 interrupt active edge 00: disabled interrupt 01: rising edge interrupt 10: falling edge interrupt 11: dual edge interrupt bit 1 ~ 0 int0s1, int0s0 : defnes int0 interrupt active edge 00: disabled interrupt 01: rising edge interrupt 10: falling edge interrupt 11: dual edge interrupt intc0 register bit 7 6 5 4 3 2 1 0 na?e ocp0f ovpf ocp1f ocp0e ovpe ocp1e emi r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 unimplemented, read as 0 bit 6 ocp0f : over current protection 0 interrupt request fag 0: no request 1: interrupt request bit 5 ovpf : over voltage protection interrupt request fag 0: no request 1: interrupt request bit 4 ocp1f : over current protection 1 interrupt request fag 0: no request 1: interrupt request bit 3 ocp0e : over current protection 0 interrupt control 0: disable 1: enable bit 2 ovpe : over voltage protection interrupt control 0: disable 1: enable bit 1 ocp1e : over current protection 1 interrupt control 0: disable 1: enable bit 0 emi : global interrupt control 0: disable 1: enable
rev. 1.30 138 de?e??e? 1?? ?01? rev. 1.30 139 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu intc1 register bit 7 6 5 4 3 2 1 0 na?e int?f int1f int0f uvpf int?e int1e int0e uvpe r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 int2f : int2 interrupt request fag 0: no request 1: interrupt request bit 6 int1f : int1 interrupt request fag 0: no request 1: interrupt request bit 5 int0f : int0 interrupt request fag 0: no request 1: interrupt request bit 4 uvpf : under voltage protection interrupt request fag 0: no request 1: interrupt request bit 3 int2e : int2 interrupt control 0: disable 1: enable bit 2 int1e : int1 interrupt control 0: disable 1: enable bit 1 int0e : int0 interrupt control 0: disable 1: enable bit 0 uvpe : under voltage protection interrupt control 0: disable 1: enable
rev. 1.30 138 de?e??e? 1?? ?01? rev. 1.30 139 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu intc2 register bit 7 6 5 4 3 2 1 0 na?e mf3f mf?f mf1f mf0f mf3e mf?e mf1e mf0e r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 mf3f : multi-function interrupt 3 request fag 0: no request 1: interrupt request bit 6 mf2f : multi-function interrupt 2 request fag 0: no request 1: interrupt request bit 5 mf1f : multi-function interrupt 1 request fag 0: no request 1: interrupt request bit 4 mf0f : multi-function interrupt 0 request fag 0: no request 1: interrupt request bit 3 mf3e : multi-function interrupt 3 control 0: disable 1: enable bit 2 mf2e : multi-function interrupt 2 control 0: disable 1: enable bit 1 mf1e : multi-function interrupt 1 control 0: disable 1: enable bit 0 mf0e : multi-function interrupt 0 control 0: disable 1: enable
rev. 1.30 1?0 de?e??e? 1?? ?01? rev. 1.30 1?1 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu intc3 register bit 7 6 5 4 3 2 1 0 na?e lvf tb1f tb0f adf lve tb1e tb0e ade r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 lvf : lvd interrupt request fag 0: no request 1: interrupt request bit 6 tb1f : time base 1 interrupt request fag 0: no request 1: interrupt request bit 5 tb0f : time base 0 interrupt request fag 0: no request 1: interrupt request bit 4 adf : a/d converter interrupt request fag 0: no request 1: interrupt request bit 3 lve : lvd interrupt control 0: disable 1: enable bit 2 tb1e : time base 1 interrupt control 0: disable 1: enable bit 1 tb0e : time base 0 interrupt control 0: disable 1: enable bit 0 ade : a/d converter interrupt control 0: disable 1: enable
rev. 1.30 1?0 de?e??e? 1?? ?01? rev. 1.30 1?1 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu mfi0 register bit 7 6 5 4 3 2 1 0 na?e def t0af t0pf dee t0ae t0pe r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7 unimplemented, read as 0 bit 6 def : data eeprom interrupt request fag 0: no request 1: interrupt request bit 5 t0af : tm0 comparator a match interrupt request fag 0: no request 1: interrupt request bit 4 t0pf : tm0 comparator p match interrupt request fag 0: no request 1: interrupt request bit 3 unimplemented, read as 0 bit 2 dee : data eeprom interrupt control 0: disable 1: enable bit 1 t0ae : tm0 comparator a match interrupt control 0: disable 1: enable bit 0 t0pe : tm0 comparator p match interrupt control 0: disable 1: enable mfi1 register bit 7 6 5 4 3 2 1 0 na?e t1af t1pf t1ae t1pe r/w r/w r/w r/w r/w por 0 0 0 0 bit 7 ~ 6 unimplemented, read as 0 bit 5 t1af : tm1 comparator a match interrupt request fag 0: no request 1: interrupt request bit 4 t1pf : tm1 comparator p match interrupt request fag 0: no request 1: interrupt request bit 3 ~ 2 unimplemented, read as 0 bit 1 t1ae : tm1 comparator a match interrupt control 0: disable 1: enable bit 0 t1pe : tm1 comparator p match interrupt control 0: disable 1: enable
rev. 1.30 1?? de?e??e? 1?? ?01? rev. 1.30 1?3 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu mfi2 register bit 7 6 5 4 3 2 1 0 na?e t?af t?pf t?ae t?pe r/w r/w r/w r/w r/w por 0 0 0 0 bit 7 ~ 6 unimplemented, read as 0 bit 5 t2af : tm2 comparator a match interrupt request fag 0: no request 1: interrupt request bit 4 t2pf : tm2 comparator p match interrupt request fag 0: no request 1: interrupt request bit 3 ~ 2 unimplemented, read as 0 bit 1 t2ae : tm2 comparator a match interrupt control 0: disable 1: enable bit 0 t2pe : tm2 comparator p match interrupt control 0: disable 1: enable mfi3 register bit 7 6 5 4 3 2 1 0 na?e t3af t3pf t3ae t3pe r/w r/w r/w r/w r/w por 0 0 0 0 bit 7 ~ 6 unimplemented, read as 0 bit 5 t3af : tm3 comparator a match interrupt request fag 0: no request 1: interrupt request bit 4 t3pf : tm3 comparator p match interrupt request fag 0: no request 1: interrupt request bit 3 ~ 2 unimplemented, read as 0 bit 1 t3ae : tm3 comparator a match interrupt control 0: disable 1: enable bit 0 t3pe : tm3 comparator p match interrupt control 0: disable 1: enable
rev. 1.30 1?? de?e??e? 1?? ?01? rev. 1.30 1?3 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu interrupt operation when the conditions for an interrupt event occur, such as a tm comparator p or comparator a match or a/d conversion completion etc, the relevant interrupt request fag will be set. whether the request fag actually generates a program jump to the relevant interrupt vector is determined by the condition of the interrupt enable bit. if the enable bit is set high then the program will jump to its relevant vector; if the enable bit is zero then although the interrupt request fag is set an actual interrupt will not be generated and the program will not jump to the relevant interrupt vector. the global interrupt enable bit, if cleared to zero, will disable all interrupts. when an interrupt is generated, the program counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. the program counter will then be loaded with a new address which will be the value of the corresponding interrupt vector. the microcontroller will then fetch its next instruction from this interrupt vector. the instruction at this vector will usually be a jmp which will jump to another section of program which is known as the interrupt service routine. here is located the code to control the appropriate interrupt. the interrupt service routine must be terminated with a reti, which retrieves the original program counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred. the various interrupt enable bits, together with their associated request flags, are shown in the accompanying diagrams with their order of priority. some interrupt sources have their own individual vector while others share the same multi-function interrupt vector. once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the global interrupt enable bit, emi bit will be cleared automatically. this will prevent any further interrupt nesting from occurring. however, if other interrupt requests occur during this interval, although the interrupt will not be immediately serviced, the request fag will still be recorded. if an interrupt requires immediate servicing while the program is already in another interrupt service routine, the emi bit should be set after entering the routine, to allow interrupt nesting. if the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is decremented. if immediate service is desired, the stack must be prevented from becoming full. in case of simultaneous requests, the accompanying diagram shows the priority that is applied. all of the interrupt request fags when set will wake-up the device if it is in sleep or idle mode, however to prevent a wake-up from occurring the corresponding fag should be set before the device is in sleep or idle mode.
rev. 1.30 1?? de?e??e? 1?? ?01? rev. 1.30 1?5 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu 0?h 0ch 10h 30h vector low p ? io ? ity high request flags ena ? le bits maste ? ena ? le request flags ena ? le bits emi auto disa ? led in isr inte ?? upt na ? e inte ?? upt na ? e emi emi emi t1af tm1 a t1ae t1pf tm1 p t1pe ocp1f ove ? cu ?? ent p ? ote ? tion 1 ocp1e ocp0f ove ? ? u ?? ent p ? ote ? tion 0 ocp0e adf a/d ade xxf legend request flag C no auto ? eset in isr xxf request flag C auto ? eset in isr xxe ena ? le bit t0af tm0 a t0pf tm0 p t0ae t0pe 18h emi int1f int1 pin int1e ?c h emi mf 3 f m. fun ? t. 3 mf 3 e 08h emi ovpf ove ? voltage p ? ote ? tion ovpe ?8h emi t ? af tm ? a t ? ae t ? pf tm ? p t ? pe mf ?f m. fun ? t. ? mf ?e t 3 af tm 3 a t 3 ae t 3 pf tm 3 p t 3 pe 1?h emi int0f int0 pin int0e def eeprom dee lvf lvd lve tb0 f ti ? e base 0 tb0 e tb1f ti ? e base 1 tb1e inte ?? upts ? ontained within multi - fun ? tion inte ?? upts emi uvpf unde ? voltage p ? ote ? tion uvpe 1ch emi int ? f int ? pin int ? e ?0h emi mf0f m. fun ? t. 0 mf0e ??h emi mf1f m. fun ? t. 1 mf1e 3?h emi 38h emi 3ch emi interrupt structure
rev. 1.30 1?? de?e??e? 1?? ?01? rev. 1.30 1?5 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu external interrupt the external interrupts are controlled by signal transitions on the pins int0~int2. an external interrupt request will take place when the external interrupt request fags, int0f~int2f, are set, which will occur when a transition, whose type is chosen by the edge select bits, appears on the external interrupt pins. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and respective external interrupt enable bit, int0e~int2e, must frst be set. additionally the correct interrupt edge type must be selected using the integ register to enable the external interrupt function and to choose the trigger edge type. as the external interrupt pins are pin-shared with i/o pins, they can only be configured as external interrupt pins if their external interrupt enable bit in the corresponding interrupt register has been set. the pin must also be setup as an input by setting the corresponding bit in the port control register. when the interrupt is enabled, the stack is not full and the correct transition type appears on the external interrupt pin, a subroutine call to the external interrupt vector, will take place. when the interrupt is serviced, the external interrupt request flags, int0f~int2f, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. note that any pull- high resistor selections on the external interrupt pins will remain valid even if the pin is used as an external interrupt input. the integ register is used to select the type of active edge that will trigger the external interrupt. a choice of either rising or falling or both edge types can be chosen to trigger an external interrupt. note that the integ register can also be used to disable the external interrupt function. uvp interrupt an uvp interrupt request will take place when the under voltage protection interrupt request fag, uvpf, is set, which occurs when the under voltage protection function detects an under voltage condition. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and under voltage protection interrupt enable bit, must frst be set. when the interrupt is enabled, the stack is not full and a low voltage condition occurs, a subroutine call to the uvp interrupt vector, will take place. when the under voltage protection interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts and the interrupt request fag will be also automatically cleared. ovp interrupt an ovp interrupt request will take place when the over voltage protection interrupt request fag, ovpf, is set, which occurs when the over voltage protection function detects an over voltage condition. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and over voltage protection interrupt enable bit, must frst be set. when the interrupt is enabled, the stack is not full and a low voltage condition occurs, a subroutine call to the ovp interrupt vector, will take place. when the over voltage protection interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts and the interrupt request fag will be also automatically cleared.
rev. 1.30 1?? de?e??e? 1?? ?01? rev. 1.30 1?7 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu ocp interrupt an ocp0, ocp1 interrupt request will take place when the over current protection 0, 1 interrupt request fag, ocp0f, ocp1f, is set, which occurs when the over current protection 0, 1 function detects an over current condition. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and over current protection 0, 1 interrupt enable bit, must frst be set. when the interrupt is enabled, the stack is not full and a low voltage condition occurs, a subroutine call to the ocp0, ocp1 interrupt vector, will take place. when the over current protection interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts and the interrupt request fag will be also automatically cleared. multi-function interrupt within the device there are four multi-function interrupts. unlike the other independent interrupts, these interrupts have no independent source, but rather are formed from other existing interrupt sources, namely the tm interrupts and eeprom interrupt. a multi-function interrupt request will take place when any of the multi-function interrupt request fags, mfnf are set. the multi-function interrupt fags will be set when any of their included functions generate an interrupt request fag. to allow the program to branch to its respective interrupt vector address, when the multi-function interrupt is enabled and the stack is not full, and either one of the interrupts contained within each of multi-function interrupt occurs, a subroutine call to one of the multi-function interrupt vectors will take place. when the interrupt is serviced, the related multi-function request flag, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. however, it must be noted that, although the multi-function interrupt fags will be automatically reset when the interrupt is serviced, the request fags from the original source of the multi-function interrupts, namely the tm interrupts and eeprom interrupt will not be automatically reset and must be manually reset by the application program. a/d converter interrupt the a/d converter interrupt is controlled by the termination of an a/d conversion process. an a/d converter interrupt request will take place when the a/d converter interrupt request fag, adf, is set, which occurs when the a/d conversion process fnishes. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and a/d interrupt enable bit, ade, must frst be set. when the interrupt is enabled, the stack is not full and the a/d conversion process has ended, a subroutine call to the a/d converter interrupt vector, will take place. when the interrupt is serviced, the a/d converter interrupt fag, adf, will be automatically cleared. the emi bit will also be automatically cleared to disable other interrupts.
rev. 1.30 1?? de?e??e? 1?? ?01? rev. 1.30 1?7 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu time base interrupts the function of the time base interrupts is to provide regular time signal in the form of an internal interrupt. they are controlled by the overfow signals from their respective timer functions. when these happens their respective interrupt request flags, tb0f or tb1f will be set. to allow the program to branch to their respective interrupt vector addresses, the global interrupt enable bit, emi and time base enable bits, tb0e or tb1e, must frst be set. when the interrupt is enabled, the stack is not full and the time base overfows, a subroutine call to their respective vector locations will take place. when the interrupt is serviced, the respective interrupt request fag, tb0f or tb1f, will be automatically reset and the emi bit will be cleared to disable other interrupts. the purpose of the time base interrupt is to provide an interrupt signal at fxed time periods. their clock sources originate from the internal clock source f tb . this f tb input clock passes through a divider, the division ratio of which is selected by programming the appropriate bits in the tbc register to obtain longer interrupt periods whose value ranges. the clock source that generates f tb , which in turn controls the time base interrupt period, can originate from several different sources, as shown in the system operating mode section. tbc register bit 7 6 5 4 3 2 1 0 na?e tbon tbck tb11 tb10 tb0? tb01 tb00 r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 1 1 1 1 1 bit 7 tbon : tb0 and tb1 control bit 0: disable 1: enable b it 6 tbck : select f tb clock 0: f tbc 1: f sys /4 bit 5 ~ 4 tb11 ~ tb10 : select time base 1 time-out period 00: 4096/f tb 01: 8192/f tb 10: 16384/f tb 11: 32768/f tb bit 3 unimplemented, read as 0 bit 2 ~ 0 tb02 ~ tb00 : select time base 0 time-out period 000: 256/f tb 001: 512/f tb 010: 1024/f tb 011: 2048/f tb 100: 4096/f tb 101: 8192/f tb 110: 16384/f tb 111: 32768/f tb                         
        
          
      time base interrupt
rev. 1.30 1?8 de?e??e? 1?? ?01? rev. 1.30 1?9 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu eeprom interrupt the eeprom interrupt is contained within the multi-function interrupt. an eeprom interrupt request will take place when the eeprom interrupt request flag, def, is set, which occurs when an eeprom write cycle ends. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and eeprom interrupt enable bit, dee, and associated multi-function interrupt enable bit, mf0e, must frst be set. when the interrupt is enabled, the stack is not full and an eeprom write cycle ends, a subroutine call to the respective eeprom interrupt vector, will take place. when the eeprom interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, however only the multi-function interrupt request fag will be also automatically cleared. as the def fag will not be automatically cleared, it has to be cleared by the application program. lvd interrupt an lvd interrupt request will take place when the lvd interrupt request fag, lvf, is set, which occurs when the low voltage detector function detects a low power supply voltage. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and low voltage interrupt enable bit, lve, must frst be set. when the interrupt is enabled, the stack is not full and a low voltage condition occurs, a subroutine call to the lvd interrupt vector, will take place. when the low voltage interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, and the lvd interrupt request fag, lvf, will be also automatically cleared. tm interrupts the standard type tm and the periodic type tms each has two interrupts. all of the tm interrupts are contained within the multi-function interrupts. for the standard type tm and the periodic type tms there are two interrupt request fags tnpf and tnaf and two enable bits tnpe and tnae. a tm interrupt request will take place when any of the tm request fags are set, a situation which occurs when a tm comparator p or comparator a match situation happens. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and the respective tm interrupt enable bit, and associated multi-function interrupt enable bit, mfnf, must frst be set. when the interrupt is enabled, the stack is not full and a tm comparator match situation occurs, a subroutine call to the relevant tm interrupt vector locations, will take place. when the tm interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, however only the related mfnf fag will be automatically cleared. as the tm interrupt request fags will not be automatically cleared, they have to be cleared by the application program. interrupt wake-up function each of the interrupt functions has the capability of waking up the microcontroller when in the sleep or idle mode. a wake-up is generated when an interrupt request fag changes from low to high and is independent of whether the interrupt is enabled or not. therefore, even though the device is in the sleep or idle mode and its system oscillator stopped, situations such as external edge transitions on the external interrupt pins or a low power supply voltage may cause their respective interrupt fag to be set high and consequently generate an interrupt. care must therefore be taken if spurious wake-up situations are to be avoided. if an interrupt wake-up function is to be disabled then the corresponding interrupt request fag should be set high before the device enters the sleep or idle mode. the interrupt enable bits have no effect on the interrupt wake-up function.
rev. 1.30 1?8 de?e??e? 1?? ?01? rev. 1.30 1?9 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu programming considerations by disabling the relevant interrupt enable bits, a requested interrupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request fag is cleared by the application program. where a certain interrupt is contained within a multi-function interrupt, then when the interrupt service routine is executed, as only the multi-function interrupt request fags, mf0f~mf3f, will be automatically cleared, the individual request flag for the function needs to be cleared by the application program. it is recommended that programs do not use the call instruction within the interrupt service subroutine. interrupts often occur in an unpredictable manner or need to be serviced immediately. if only one stack is left and the interrupt is not well controlled, the original control sequence will be damaged once a call subroutine is executed in the interrupt subroutine. every interrupt has the capability of waking up the microcontroller when it is in sleep or idle mode, the wake up being generated when the interrupt request fag changes from low to high. if it is required to prevent a certain interrupt from waking up the microcontroller then its respective request fag should be frst set high before enter sleep or idle mode. as only the program counter is pushed onto the stack, then when the interrupt is serviced, if the contents of the accumulator, status register or other registers are altered by the interrupt service program, their contents should be saved to the memory at the beginning of the interrupt service routine. to return from an interrupt subroutine, either a ret or reti instruction may be executed. the reti instruction in addition to executing a return to the main program also automatically sets the emi bit high to allow further interrupts. the ret instruction however only executes a return to the main program leaving the emi bit in its present zero state and therefore disabling the execution of further interrupts.
rev. 1.30 150 de?e??e? 1?? ?01? rev. 1.30 151 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu low voltage detector C lvd the device has a low voltage detector function, also known as lvd. this enable s the device to monitor the power supply voltage, v dd , and provide s a warning signal should it fall below a certain level. this function may be especially useful in battery applications where the supply voltage will gradually reduce as the battery ages, as it allows an early warning battery low signal to be generated. the low voltage detector also has the capability of generating an interrupt signal. lvd register the low voltage detector function is controlled using a single register with the name lvdc. three bits in this register, vlvd2~vlvd0, are used to select one of fve fxed voltages below which a low voltage condition will be detemined. a low voltage condition is indicated when the lvdo bit is set. if the lvdo bit is low, this indicates that the v dd voltage is above the preset low voltage value. the lvden bit is used to control the overall on/off function of the low voltage detector. setting the bit high will enable the low voltage detector. clearing the bit to zero will switch off the internal low voltage detector circuits. as the low voltage detector will consume a certain amount of power, it may be desirable to switch off the circuit when not in use, an important consideration in power sensitive battery powered applications. lvdc register bit 7 6 5 4 3 2 1 0 na?e lvdo lvden vlvd ? vlvd1 vlvd0 r/w r r/w r/w r/w r/w por 0 0 0 0 0 bit 7 ~ 6 unimplemented, read as 0 bit 5 lvdo : lvd output flag 0: no low voltage detect 1: low voltage detect bit 4 lvden : low voltage detector control 0: disable 1: enable bit 3 unimplemented, read as 0 bit 2~0 vlvd2 ~ vlvd0 : select lvd voltage 000: undefned 001: undefned 010: undefned 011: 2.7v 100: 3.0v 101: 3.3v 110: 3.6v 111: 4.0v
rev. 1.30 150 de?e??e? 1?? ?01? rev. 1.30 151 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu lvd operation the low voltage detector function operates by comparing the power supply voltage, v dd , with a pre-specifed voltage level stored in the lvdc register. this has a range of between 2. 7 v and 4.0v. when the power supply voltage, v dd , falls below this pre-determined value, the lvdo bit will be set high indicating a low power supply voltage condition. the low voltage detector function is supplied by a reference voltage which will be automatically enabled. when the device is powered down the low voltage detector will remain active if the lvden bit is high. after enabling the low voltage detector, a time delay t lvds should be allowed for the circuitry to stabilise before reading the lvdo bit. note also that as the v dd voltage may rise and fall rather slowly, at the voltage nears that of v lvd , there may be multiple bit lvdo transitions.              lvd operation the low voltage detector also has its own interrupt, providing an alternative means of low voltage detection, in addition to polling the lvdo bit. the interrupt will only be generated after a delay of t lvd after the lvdo bit has been set high by a low voltage condition. when the device is powered down the low voltage detector will remain active if the lvden bit is high. in this case, the lvf interrupt request fag will be set, causing an interrupt to be generated if v dd falls below the preset lvd voltage. this will cause the device to wake-up from the sleep or idle mode, however if the low voltage detector wake up function is not required then the lvf fag should be frst set high before the device enters the sleep or idle mode.
rev. 1.30 15? de?e??e? 1?? ?01? rev. 1.30 153 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu scom function for lcd the device has the capability of driving external lcd panels. the common pins for lcd driving, scom0~scom3, are pin shared with certain pin on the pb0, pa4, pa3 and pa5 port. the lcd signals (com and seg) are generated using the application program. lcd operation an external lcd panel can be driven using this device by confguring the pb0, pa4, pa3 and pa5 pins as common pins and using other output ports lines as segment pins. the lcd driver function is controlled using the scomc register which in addition to controlling the overall on/off function also controls the bias voltage setup function. this enables the lcd com driver to generate the necessary v dd /2 voltage levels for lcd 1/2 bias operation. the scomen bit in the scomc register is the overall master control for the lcd driver, however this bit is used in conjunction with the comnen bits to select which port c pins are used for lcd driving. note that the port control register does not need to frst setup the pins as outputs to enable the lcd driver operation.                     
     lcd com bias control scomen comnen pin function o/p level 0 x i/o 0 o? 1 1 0 i/o 0 o? 1 1 1 scomn v dd /? output control
rev. 1.30 15? de?e??e? 1?? ?01? rev. 1.30 153 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu lcd bias control the lcd com driver enables a range of selections to be provided to suit the requirement of the lcd panel which is being used. the bias resistor choice is implemented using the isel1 and isel0 bits in the scomc register. scomc register bit 7 6 5 4 3 2 1 0 na?e isel1 isel0 scomen com3en com?en com1en com0en r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 reserved bit 0: correct level - bit must be reset to zero for correct operation 1: unpredictable operation - bit must not be set high bit 6~5 isel1 ~ isel0 : select scom typical bias current (v dd =5v) 00: 25a 01: 50a 10: 100a 11: 200a bit4 scomen : scom module control 0: disable 1: enable bit3 com3en : pa5 or scom3 selection 0: gpio 1: scom3 bit 2 com2en : pa3 or scom2 selection 0: gpio 1: scom2 bit 1 com1en : pa4 or scom1 selection 0: gpio 1: scom1 bit 0 com0en : pb0 or scom0 selection 0: gpio 1: scom0
rev. 1.30 15? de?e??e? 1?? ?01? rev. 1.30 155 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu application circuit usb i/p HT45F4N lithiu? batte?y x 1 + 50? an ocp io vdd outnl outnh ouvp io io ocp io io io vss usb o/p an dapwr/vref tl?31b 105 10? 105 ?.5v io/scom lcd/led panel v dd 51k 1k 50? usb i/p ht45fh4n lithiu? batte?y x ? + 50? an ocp io vcc ax/bx cx/dx 50? ouvp io io ocp io io io io io vss usb o/p io an dapwr/vref rt1 50k / ?5 c 51k tl?31b 1k 105 10? 105 v dd t ?.5v v5 vdd io/scom lcd/led panel
rev. 1.30 15? de?e??e? 1?? ?01? rev. 1.30 155 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu instruction set introduction central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to perform certain operations. in the case of holtek microcontroller, a comprehensive and fexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. for easier understanding of the various instruction codes, they have been subdivided into several functional groupings. instruction timing most instructions are implemented within one instruction cycle. the exceptions to this are branch, call, or table read instructions where two instruction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8mhz system oscillator, most instructions would be implemented within 0.5s and branch or call instructions would be implemented within 1s. although instructions which require one more cycle to implement are generally limited to the jmp, call, ret, reti and table read instructions, it is important to realize that any other instructions which involve manipulation of the program counter low register or pcl will also take one more cycle to implement. as instructions which change the contents of the pcl will imply a direct jump to that new address, one more cycle will be required. examples of such instructions would be clr pcl or mov pcl, a. for the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. moving and transferring data the transfer of data within the microcontroller program is one of the most frequently used operations. making use of three kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specifc immediate data directly into the accumulator. one of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. arithmetic operations the ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. within the holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for subtraction. the increment and decrement instructions inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specifed.
rev. 1.30 15? de?e??e? 1?? ?01? rev. 1.30 157 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu logical and rotate operation the standard logical operations such as and, or, xor and cpl all have their own instruction within the holtek microcontroller instruction set. as with the case of most instructions involving data manipulation, data must pass through the accumulator which may involve additional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. different rotate instructions exist depending on program requirements. rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the carry bit from where it can be examined and the necessary serial bit set high or low. another application which rotate data operations are used is to implement multiplication and division calculations. branches and control transfer program branching takes the form of either jumps to specifed locations using the jmp instruction or to a subroutine using the call instruction. they differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the subroutine has been carried out. this is done by placing a return instruction ret in the subroutine which will cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping off point as in the case of the call instruction. one special and extremely useful set of branch instructions are the conditional branches. here a decision is frst made regarding the condition of a certain data memory or individual bits. depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. these instructions are the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits. bit operations the ability to provide single bit operations on data memory is an extremely fexible feature of all holtek microcontrollers. this feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the set [m].i or clr [m].i instructions respectively. the feature removes the need for programmers to frst read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write process is taken care of automatically when these bit operation instructions are used. table read operations data storage is normally implemented by using registers. however, when working with large amounts of fxed data, the volume involved often makes it inconvenient to store the fxed data in the data memory. to overcome this problem, holtek microcontrollers allow an area of program memory to be set as a table where data can be directly stored. a set of easy to use instructions provides the means by which this fixed data can be referenced and retrieved from the program memory. other operations in addition to the above functional instructions, a range of other instructions also exist such as the halt instruction for power-down operations and instructions to control the operation of the watchdog timer for reliable program operations under extreme electric or electromagnetic environments. for their relevant operations, refer to the functional related sections.
rev. 1.30 15? de?e??e? 1?? ?01? rev. 1.30 157 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu instruction set summary the following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. table conventions x: bits immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address mnemonic description cycles flag affected arithmetic add a?[?] add data me?o? y to acc 1 z? c? ac? ov addm a?[?] add acc to data me ?o?y 1 note z? c? ac? ov add a?x add i?? ediate data to acc 1 z? c? ac? ov adc a?[?] add data me?o? y to acc with ca??y 1 z? c? ac? ov adcm a?[?] add acc to data ?e?o?y with ca??y 1 note z? c? ac? ov sub a?x su?t?a?t i??ediate data f?o? the acc 1 z? c? ac? ov sub a?[?] su?t?a?t data me?o?y f?o? acc 1 z? c? ac? ov subm a?[?] su?t?a?t data me?o?y f?o? acc with ?esult in data me?o?y 1 note z? c? ac? ov sbc a?[?] su?t?a?t data me?o?y f?o? acc with ca??y 1 z? c? ac? ov sbcm a?[?] su?t?a?t data me?o?y f?o? acc with ca??y ? ?esult in data me?o?y 1 note z? c? ac? ov daa [ ?] de?i? al adjust acc fo? addition with ?esult in data me?o?y 1 note c logic operation and a?[?] logi? al and data me?o? y to acc 1 z or a?[?] logi?al or data me?o? y to acc 1 z xor a?[?] logi?al xor data me?o? y to acc 1 z andm a?[?] logi? al and acc to data me?o?y 1 note z orm a?[?] logi? al or acc to data me?o?y 1 note z xorm a?[?] logi? al xor acc to data me?o?y 1 note z and a?x logi? al and i?? ediate data to acc 1 z or a?x logi?al or i?? ediate data to acc 1 z xor a?x logi?al xor i?? ediate data to acc 1 z cpl [ ?] co?ple?ent data me?o?y 1 note z cpla [ ?] co?ple?ent data me?o?y with ? esult in acc 1 z increment & decrement inca [ ?] in??e?ent data me?o?y with ? esult in acc 1 z inc [?] in??e?ent data me?o?y 1 note z deca [ ?] de??e?ent data me?o?y with ? esult in acc 1 z dec [?] de??e?ent data me?o?y 1 note z rotate rra [ ?] rotate data me?o?y ?ight with ? esult in acc 1 none rr [?] rotate data me?o?y ?ight 1 note none rrca [ ?] rotate data me?o?y ?ight th?ough ca??y with ? esult in acc 1 c rrc [?] rotate data me?o?y ?ight th?ough ca??y 1 note c rla [ ?] rotate data me?o?y left with ? esult in acc 1 none rl [ ?] rotate data me?o?y left 1 note none rlca [ ?] rotate data me?o?y left th?ough ca??y with ? esult in acc 1 c rlc [?] rotate data me?o?y left th?ough ca??y 1 note c
rev. 1.30 158 de?e??e? 1?? ?01? rev. 1.30 159 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu mnemonic description cycles flag affected data move mov a ?[?] move data me?o? y to acc 1 none mov [?]?a move acc to data me ?o?y 1 note none mov a ?x move i?? ediate data to acc 1 none bit operation clr [?].i clea? ?it of data me?o?y 1 note none set [ ?].i set ?it of data me?o?y 1 note none branch jmp add ? ju?p un?onditionally ? none sz [?] skip if data me?o?y is ze?o 1 note none sza [ ?] skip if data me?o?y is ze?o with data ?ove? ent to acc 1 note none sz [?].i skip if ?it i of data me?o?y is ze?o 1 note none snz [?].i skip if ?it i of data me?o?y is not ze?o 1 note none siz [?] skip if in??e?ent data me?o?y is ze?o 1 note none sdz [?] skip if de??e?ent data me?o?y is ze?o 1 note none siza [ ?] skip if in??e?ent data me?o?y is ze?o with ? esult in acc 1 note none sdza [ ?] skip if de??e?ent data me?o?y is ze?o with ? esult in acc 1 note none call add ? su??outine ?all ? none ret retu?n f?o? su??outine ? none ret a ?x retu?n f?o? su??outine and load i?? ediate data to acc ? none reti retu?n f?o? inte??upt ? none table read tabrd [ ?] read table (specifc page) to tblh and data memory ? note none tabrdc [ ?] read ta?le (?u?? ent page) to tblh and data me?o?y ? note none tabrdl [ ?] read ta? le (last page) to tblh and data me?o?y ? note none miscellaneous nop no ope?ation 1 none clr [?] clea? data me?o?y 1 note none set [ ?] set data me?o?y 1 note none clr wdt clea? wat? hdog ti?e? 1 to ? pdf clr wdt1 p?e-?lea? wat? hdog ti?e? 1 to ? pdf clr wdt? p?e-?lea? wat? hdog ti?e? 1 to ? pdf swap [ ?] swap ni??les of data me?o?y 1 note none swapa [ ?] swap ni??les of data me?o?y with ? esult in acc 1 none halt ente? powe? down ?ode 1 to ? pdf note: 1. for skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. any instruction which changes the contents of the pcl will also require 2 cycles for execution. 3. for the clr wdt1 and clr wdt2 instructions the to and pdf flags may be affected by the execution status. the to and pdf flags are cleared after both clr wdt1 and clr wdt2 instructions are consecutively executed. otherwise the to and pdf fags remain unchanged.
rev. 1.30 158 de?e??e? 1?? ?01? rev. 1.30 159 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu instruction defnition adc a,[m] add data memory to acc with carry description the contents of the specifed data memory, accumulator and the carry fag are added. the result is stored in the accumulator. operation acc acc + [m] + c affected fag(s) ov, z, ac, c adcm a,[m] add acc to data memory with carry description the contents of the specifed data memory, accumulator and the carry fag are added. the result is stored in the specifed data memory. operation [m] acc + [m] + c affected fag(s) ov, z, ac, c add a,[m] add data memory to acc description the contents of the specifed data memory and the accumulator are added. the result is stored in the accumulator. operation acc acc + [m] affected fag(s) ov, z, ac, c add a,x add immediate data to acc description the contents of the accumulator and the specifed immediate data are added. the result is stored in the accumulator. operation acc acc + x affected fag(s) ov, z, ac, c addm a,[m] add acc to data memory description the contents of the specifed data memory and the accumulator are added. the result is stored in the specifed data memory. operation [m] acc + [m] affected fag(s) ov, z, ac, c and a,[m] logical and data memory to acc description data in the accumulator and the specifed data memory perform a bitwise logical and operation. the result is stored in the accumulator. operation acc acc and [m] affected fag(s) z and a,x logical and immediate data to acc description data in the accumulator and the specifed immediate data perform a bit wise logical and operation. the result is stored in the accumulator. operation acc acc and x affected fag(s) z andm a,[m] logical and acc to data memory description data in the specifed data memory and the accumulator perform a bitwise logical and operation. the result is stored in the data memory. operation [m] acc and [m] affected fag(s) z
rev. 1.30 1?0 de?e??e? 1?? ?01? rev. 1.30 1?1 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu call addr subroutine call description unconditionally calls a subroutine at the specifed address. the program counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the stack. the specifed address is then loaded and the program continues execution from this new address. as this instruction requires an additional operation, it is a two cycle instruction. operation stack program counter + 1 program counter addr affected fag(s) none clr [m] clear data memory description each bit of the specifed data memory is cleared to 0. operation [m] 00h affected fag(s) none clr [m].i clear bit of data memory description bit i of the specifed data memory is cleared to 0. operation [m].i 0 affected fag(s) none clr wdt clear watchdog timer description the to, pdf fags and the wdt are all cleared. operation wdt cleared to 0 pdf 0 affected fag(s) to, pdf clr wdt1 pre-clear watchdog timer description the to, pdf fags and the wdt are all cleared. note that this instruction works in conjunction with clr wdt2 and must be executed alternately with clr wdt2 to have effect. repetitively executing this instruction without alternately executing clr wdt2 will have no effect. operation wdt cleared to 0 pdf 0 affected fag(s) to, pdf clr wdt2 pre-clear watchdog timer description the to, pdf fags and the wdt are all cleared. note that this instruction works in conjunction with clr wdt1 and must be executed alternately with clr wdt1 to have effect. repetitively executing this instruction without alternately executing clr wdt1 will have no effect. operation wdt cleared to 0 pdf 0 affected fag(s) to, pdf cpl [m] complement data memory description each bit of the specifed data memory is logically complemented (1s complement). bits which previously contained a 1 are changed to 0 and vice versa. operation [m] [m] affected fag(s) z
rev. 1.30 1?0 de?e??e? 1?? ?01? rev. 1.30 1?1 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu cpla [m] complement data memory with result in acc description each bit of the specifed data memory is logically complemented (1s complement). bits which previously contained a 1 are changed to 0 and vice versa. the complemented result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc [m] affected fag(s) z daa [m] decimal-adjust acc for addition with result in data memory description convert the contents of the accumulator value to a bcd (binary coded decimal) value resulting from the previous addition of two bcd variables. if the low nibble is greater than 9 or if ac fag is set, then a value of 6 will be added to the low nibble. otherwise the low nibble remains unchanged. if the high nibble is greater than 9 or if the c fag is set, then a value of 6 will be added to the high nibble. essentially, the decimal conversion is performed by adding 00h, 06h, 60h or 66h depending on the accumulator and fag conditions. only the c fag may be affected by this instruction which indicates that if the original bcd sum is greater than 100, it allows multiple precision decimal addition. operation [m] acc + 00h or [m] acc + 06h or [m] acc + 60h or [m] acc + 66h affected fag(s) c dec [m] decrement data memory description data in the specifed data memory is decremented by 1. operation [m] [m] ? 1 affected fag(s) z deca [m] decrement data memory with result in acc description data in the specifed data memory is decremented by 1. the result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc [m] ? 1 affected fag(s) z halt enter power down mode description this instruction stops the program execution and turns off the system clock. the contents of the data memory and registers are retained. the wdt and prescaler are cleared. the power down fag pdf is set and the wdt time-out fag to is cleared. operation to 0 pdf 1 affected fag(s) to, pdf inc [m] increment data memory description data in the specifed data memory is incremented by 1. operation [m] [m] + 1 affected fag(s) z inca [m] increment data memory with result in acc description data in the specifed data memory is incremented by 1. the result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc [m] + 1 affected fag(s) z
rev. 1.30 1?? de?e??e? 1?? ?01? rev. 1.30 1?3 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu jmp addr jump unconditionally description the contents of the program counter are replaced with the specifed address. program execution then continues from this new address. as this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. operation program counter addr affected fag(s) none mov a,[m] move data memory to acc description the contents of the specifed data memory are copied to the accumulator. operation acc [m] affected fag(s) none mov a,x move immediate data to acc description the immediate data specifed is loaded into the accumulator. operation acc x affected fag(s) none mov [m],a move acc to data memory description the contents of the accumulator are copied to the specifed data memory. operation [m] acc affected fag(s) none nop no operation description no operation is performed. execution continues with the next instruction. operation no operation affected fag(s) none or a,[m] logical or data memory to acc description data in the accumulator and the specifed data memory perform a bitwise logical or operation. the result is stored in the accumulator. operation acc acc or [m] affected fag(s) z or a,x logical or immediate data to acc description data in the accumulator and the specifed immediate data perform a bitwise logical or operation. the result is stored in the accumulator. operation acc acc or x affected fag(s) z orm a,[m] logical or acc to data memory description data in the specifed data memory and the accumulator perform a bitwise logical or operation. the result is stored in the data memory. operation [m] acc or [m] affected fag(s) z ret return from subroutine description the program counter is restored from the stack. program execution continues at the restored address. operation program counter stack affected fag(s) none
rev. 1.30 1?? de?e??e? 1?? ?01? rev. 1.30 1?3 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu ret a,x return from subroutine and load immediate data to acc description the program counter is restored from the stack and the accumulator loaded with the specifed immediate data. program execution continues at the restored address. operation program counter stack acc x affected fag(s) none reti return from interrupt description the program counter is restored from the stack and the interrupts are re-enabled by setting the emi bit. emi is the master interrupt global enable bit. if an interrupt was pending when the reti instruction is executed, the pending interrupt routine will be processed before returning to the main program. operation program counter stack emi 1 affected fag(s) none rl [m] rotate data memory left description the contents of the specifed data memory are rotated left by 1 bit with bit 7 rotated into bit 0. operation [m].(i+1) [m].i; (i=0~6) [m].0 [m].7 affected fag(s) none rla [m] rotate data memory left with result in acc description the contents of the specifed data memory are rotated left by 1 bit with bit 7 rotated into bit 0. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; (i=0~6) acc.0 [m].7 affected fag(s) none rlc [m] rotate data memory left through carry description the contents of the specifed data memory and the carry fag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry fag is rotated into bit 0. operation [m].(i+1) [m].i; (i=0~6) [m].0 c c [m].7 affected fag(s) c rlca [m] rotate data memory left through carry with result in acc description data in the specifed data memory and the carry fag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry fag is rotated into the bit 0. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; (i=0~6) acc.0 c c [m].7 affected fag(s) c rr [m] rotate data memory right description the contents of the specifed data memory are rotated right by 1 bit with bit 0 rotated into bit 7. operation [m].i [m].(i+1); (i=0~6) [m].7 [m].0 affected fag(s) none
rev. 1.30 1?? de?e??e? 1?? ?01? rev. 1.30 1?5 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu rra [m] rotate data memory right with result in acc description data in the specifed data memory and the carry fag are rotated right by 1 bit with bit 0 rotated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i=0~6) acc.7 [m].0 affected fag(s) none rrc [m] rotate data memory right through carry description the contents of the specifed data memory and the carry fag are rotated right by 1 bit. bit 0 replaces the carry bit and the original carry fag is rotated into bit 7. operation [m].i [m].(i+1); (i=0~6) [m].7 c c [m].0 affected fag(s) c rrca [m] rotate data memory right through carry with result in acc description data in the specifed data memory and the carry fag are rotated right by 1 bit. bit 0 replaces the carry bit and the original carry fag is rotated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i=0~6) acc.7 c c [m].0 affected fag(s) c sbc a,[m] subtract data memory from acc with carry description the contents of the specifed data memory and the complement of the carry fag are subtracted from the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. operation acc acc ? [m] ? c affected fag(s) ov, z, ac, c sbcm a,[m] subtract data memory from acc with carry and result in data memory description the contents of the specifed data memory and the complement of the carry fag are subtracted from the accumulator. the result is stored in the data memory. note that if the result of subtraction is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. operation [m] acc ? [m] ? c affected fag(s) ov, z, ac, c sdz [m] skip if decrement data memory is 0 description the contents of the specifed data memory are frst decremented by 1. if the result is 0 the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m] ? 1 skip if [m]=0 affected fag(s) none
rev. 1.30 1?? de?e??e? 1?? ?01? rev. 1.30 1?5 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu sdza [m] skip if decrement data memory is zero with result in acc description the contents of the specifed data memory are frst decremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specifed data memory contents remain unchanged. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation acc [m] ? 1 skip if acc=0 affected fag(s) none set [m] set data memory description each bit of the specifed data memory is set to 1. operation [m] ffh affected fag(s) none set [m].i set bit of data memory description bit i of the specifed data memory is set to 1. operation [m].i 1 affected fag(s) none siz [m] skip if increment data memory is 0 description the contents of the specifed data memory are frst incremented by 1. if the result is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m] + 1 skip if [m]=0 affected fag(s) none siza [m] skip if increment data memory is zero with result in acc description the contents of the specifed data memory are frst incremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specifed data memory contents remain unchanged. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m] + 1 skip if acc=0 affected fag(s) none snz [m].i skip if bit i of data memory is not 0 description if bit i of the specifed data memory is not 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is 0 the program proceeds with the following instruction. operation skip if [m].i 0 affected fag(s) none sub a,[m] subtract data memory from acc description the specifed data memory is subtracted from the contents of the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. operation acc acc ? [m] affected fag(s) ov, z, ac, c
rev. 1.30 1?? de?e??e? 1?? ?01? rev. 1.30 1?7 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu subm a,[m] subtract data memory from acc with result in data memory description the specifed data memory is subtracted from the contents of the accumulator. the result is stored in the data memory. note that if the result of subtraction is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. operation [m] acc ? [m] affected fag(s) ov, z, ac, c sub a,x subtract immediate data from acc description the immediate data specifed by the code is subtracted from the contents of the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. operation acc acc ? x affected fag(s) ov, z, ac, c swap [m] swap nibbles of data memory description the low-order and high-order nibbles of the specifed data memory are interchanged. operation [m].3~[m].0 ? [m].7~[m].4 affected fag(s) none swapa [m] swap nibbles of data memory with result in acc description the low-order and high-order nibbles of the specifed data memory are interchanged. the result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc.3~acc.0 [m].7~[m].4 acc.7~acc.4 [m].3~[m].0 affected fag(s) none sz [m] skip if data memory is 0 description if the contents of the specifed data memory is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation skip if [m]=0 affected fag(s) none sza [m] skip if data memory is 0 with data movement to acc description the contents of the specifed data memory are copied to the accumulator. if the value is zero, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m] skip if [m]=0 affected fag(s) none sz [m].i skip if bit i of data memory is 0 description if bit i of the specifed data memory is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation skip if [m].i=0 affected fag(s) none
rev. 1.30 1?? de?e??e? 1?? ?01? rev. 1.30 1?7 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu tabrd [m] read table (specifc page) to tblh and data memory description the low byte of the program code (specifc page) addressed by the table pointer pair (tbhp and tblp) is moved to the specifed data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected fag(s) none tabrdc [m] read table (current page) to tblh and data memory description the low byte of the program code (current page) addressed by the table pointer (tblp) is moved to the specifed data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected fag(s) none tabrdl [m] read table (last page) to tblh and data memory description the low byte of the program code (last page) addressed by the table pointer (tblp) is moved to the specifed data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected fag(s) none xor a,[m] logical xor data memory to acc description data in the accumulator and the specifed data memory perform a bitwise logical xor operation. the result is stored in the accumulator. operation acc acc xor [m] affected fag(s) z xorm a,[m] logical xor acc to data memory description data in the specifed data memory and the accumulator perform a bitwise logical xor operation. the result is stored in the data memory. operation [m] acc xor [m] affected fag(s) z xor a,x logical xor immediate data to acc description data in the accumulator and the specifed immediate data perform a bitwise logical xor operation. the result is stored in the accumulator. operation acc acc xor x affected fag(s) z
rev. 1.30 1?8 de?e??e? 1?? ?01? rev. 1.30 1?9 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu package information note that the package information provided here is for consultation purposes only. as this information may be updated at regular intervals users are reminded to consult the holtek website for the latest version of the package/carton information . additional supplementary information with regard to packaging is listed below. click on the relevant section to be transferred to the relevant website page. ? package information (include outline dimensions, product tape and reel specifcations) ? the operation instruction of packing materials ? carton information
rev. 1.30 1?8 de?e??e? 1?? ?01? rev. 1.30 1?9 de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu 28-pin ssop (150 mil) outline dimensions               symbol dimensions in inch min. nom. max. a 0.?3? bsc b 0.15? bsc c 0.008 0.01? c 0.390 bsc d 0.0?9 e 0.0?5 bsc f 0.00? 0.0098 g 0.01? 0.050 h 0.00? 0.010 0 8 symbol dimensions in mm min. nom. max. a ?.0 bsc b 3.9 bsc c 0.?0 0.30 c 9.9 bsc d 1.75 e 0.?35 bsc f 0.10 0.?5 g 0.?1 1.?7 h 0.10 0.?5 0 8
rev. 1.30 170 de?e??e? 1?? ?01? rev. 1.30 pb de?e??e? 1?? ?01? HT45F4N/ht45fh4n power bank flash mcu HT45F4N/ht45fh4n power bank flash mcu copy?ight ? ?01? ? y holtek semiconductor inc. the info?? ation appea?ing in this data sheet is ?elieved to ?e a??u? ate at the ti? e of pu ?li? ation. howeve ?? holtek assu? es no ?esponsi? ility a? ising f?o? the use of the specifcations described. the applications mentioned herein are used solely fo? the pu?pose of illust?ation and holtek ?akes no wa??anty o? ?ep?esentation that su? h appli? ations will ? e suita? le without fu?the? ?odifi?ation? no? ?e?o?? ends the use of its p?odu?ts fo? appli?ation that ?ay p?esent a ?isk to hu?an life due to ? alfun?tion o? othe? wise. holtek's p?odu? ts a? e not autho?ized fo? use as ?? iti? al ?o?ponents in life suppo?t devi?es o? syste?s. holtek ?ese?ves the ?ight to alte? its products without prior notifcation. for the most up-to-date information, please visit ou? we? site at http://www.holtek.?o? .tw.


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